search for: machinepipeliner

Hi, I am extending LLVM for HPC applications. As one of them, I am trying to make MachinePipeliner available on AArch64 + Scalable Vector Extension environment. MachinePipeliner is currently used only by Hexagon CPU. Since it is a very portable implementation, I think that it will actually work just by adding a little code for many CPUs(See Code [2]). The current MachinePipeliner is written on...

Sorry to bring this thread from 3 months ago back, but I’m running into this issue too. I do see that shouldIgnore is not called in the MachinePipeliner, however, James’ comment doesn’t really resolve the issue or make the story any clearer. My summary of the comment is: “Hexagon and PPC9 do not need to ignore any instructions. However, in the case that you do, such as when the indvar update is explicit, this function is provided to allow the targ...

...rs, James On Tue, 8 Sep 2020 at 23:02, Nagurne, James <j-nagurne at ti.com> wrote: > I greatly appreciate you going back to gather that intel, James. It > actually helps my understanding of the whole pipeliner puzzle quite a bit! > > > > I did identify, like you, that the MachinePipeliner pass (more precisely, > SwingSchedulerDAG) was fairly rigid in that the target doesn’t get much of > a say in some heuristics or in the generation of the result loop. I’m > definitely still in a learning phase and am poking around to see where we > can customize some things. It might ve...

Hi all, I think there is a mistake in the machinepipeliner interface. In the TargetInstrInfo.h in the class PipelinerLoopInfo there is a function "bool shouldIgnoreForPipelining(const MachineInstr *MI)". The description says that if this function returns true for a given MachineInstr it will not be pipelined. However in reality it is not ign...

Hi James, Having not worked on this for circa one year I've gone and refreshed my memory. We have a pretty capable implementation of swing modulo scheduling downstream, distinct from the MachinePipeliner implementation. Historically, MachinePipeliner had very tight coupling between the finding of a suitable schedule and emitting the code that adheres to that schedule. I spent quite a bit of time separating the two; this led to the "ModuloSchedule" and "ModuloScheduleExpander" c...

Hi Brendan (and friends of MachinePipeliner, +llvm-dev for openness), Over the past week or so I've been attempting to extend the MachinePipeliner to support different idioms of code generation. To make this a bit more concrete, there are two areas where the currently generated code could be improved depending on architecture: 1) The...

...intrusive modification. > > > > JB > > > > *From:* Jinsong Ji [mailto:jji at us.ibm.com] > *Sent:* Thursday, September 3, 2020 10:03 AM > *To:* Nagurne, James; jmolloy at google.com > *Cc:* llvm-dev at lists.llvm.org; Sander > *Subject:* [EXTERNAL] RE: [llvm-dev] Machinepipeliner interface. > shouldIgnoreForPipelining, actually not ignoring. > > > > As I mentioned before, > this API was introduced by James, mostly for his out-of-tree > implementations, > the in tree implementation NEVER implement it. > > If it is causing confusion, I think we h...

Hi, I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp. First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes. Why not put Mach...

...n Power Compiler Development E-mail: jji at us.ibm.com From: James Molloy <james at jamesmolloy.co.uk> To: LLVM Dev <llvm-dev at lists.llvm.org>, jji at us.ibm.com, bcahoon at quicinc.com, Hal Finkel <hfinkel at anl.gov> Date: 07/15/2019 06:16 AM Subject: [EXTERNAL] MachinePipeliner refactoring Hi Brendan (and friends of MachinePipeliner, +llvm-dev for openness), Over the past week or so I've been attempting to extend the MachinePipeliner to support different idioms of code generation. To make this a bit more concrete, there are two areas where the currently generated...

Hello, I'm working on integrating the MachinePipeliner.cpp pass into our VLIW backend, and so far we've managed to get it working with some nice speedups. Unlike Hexagon however, our backend doesn't generate hardware loop instructions and so all our loops are a combination of induction variables, comparisons and branches. So when it came to imp...

Hi all, I want to generate assembly code using Swing Modulo Scheduling in LLVM for many ALU (May could be Adders, multilayer ......), I need some help how I can do that, which commend I run? Also if possible more information about the scheduling and the register location ......, and which pass responsible about that, and which LLVM version support Swing Modulo Scheduling. Thank you. Regards

...nks, Brendon From: James Molloy <james at jamesmolloy.co.uk> Sent: Monday, July 15, 2019 11:05 AM To: Jinsong Ji <jji at us.ibm.com> Cc: Brendon Cahoon <bcahoon at quicinc.com>; Hal Finkel <hfinkel at anl.gov>; LLVM Dev <llvm-dev at lists.llvm.org> Subject: [EXT] Re: MachinePipeliner refactoring Hi Jingsong, Thanks for testing out the prototype! I'm not surprised there are errors in that version; it's not 100% ready yet (mainly a demonstrator for the path I'd like to take). I'm really trying to work out if it makes sense to try and incrementally get from the c...

...om: zhangqiang (CO) [mailto:zhangqiang75 at huawei.com] Sent: Thursday, May 25, 2017 3:33 AM To: llvm-dev at lists.llvm.org Cc: bcahoon at codeaurora.org Subject: Some questions about software pipeline in LLVM 4.0.0 Hi, I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp. First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes. Why not put...

I want the optimization to be turned on at -O1 and above. In my case, it is a target independent back-end pass. (Eg: MachinePipeliner) On 2017-01-04 18:10, Mehdi Amini wrote: >> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> >> I see the BackendUtil.cpp of Clang creates the TargetMachine with >> the optimization level based on below men...

...seems best for your specific pass. Hope that helps! Jessica Paquette > On Jan 5, 2017, at 8:12 AM, via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I want the optimization to be turned on at -O1 and above. > In my case, it is a target independent back-end pass. (Eg: > MachinePipeliner) > > > On 2017-01-04 18:10, Mehdi Amini wrote: >>> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev >>> <llvm-dev at lists.llvm.org> wrote: >>> I see the BackendUtil.cpp of Clang creates the TargetMachine with >>> the optimization l...

...; Hope that helps! > > Jessica Paquette > >> On Jan 5, 2017, at 8:12 AM, via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> I want the optimization to be turned on at -O1 and above. >> In my case, it is a target independent back-end pass. (Eg: >> MachinePipeliner) >> >> >> On 2017-01-04 18:10, Mehdi Amini wrote: >>>> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev >>>> <llvm-dev at lists.llvm.org> wrote: >>>> I see the BackendUtil.cpp of Clang creates the TargetMachine with >&gt...

...mple, needs to understand what legalization will later do - it's the best we can do right now, but it's a mess). If we had better loop analysis at the MI level, this would be much better. We already have some interesting MI-level passes that do interesting things with loops (lib/CodeGen/MachinePipeliner.cpp, for example). I think that we should have the same semantics here on both the IR level and the MI level (whatever they are). Having different semantics in this regard is going to be confusing (and lead to subtle bugs because optimizations valid in one part of the pipeline will be invalid i...

I see the BackendUtil.cpp of Clang creates the TargetMachine with the optimization level based on below mentioned logic CodeGenOpt::Level OptLevel = CodeGenOpt::Default; switch (CodeGenOpts.OptimizationLevel) { default: break; case 0: OptLevel = CodeGenOpt::None; break; case 3: OptLevel = CodeGenOpt::Aggressive; break; } As per my understanding, the correspondence between

...> > >>> On Jan 5, 2017, at 8:12 AM, via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > >>> > >>> I want the optimization to be turned on at -O1 and above. > >>> In my case, it is a target independent back-end pass. (Eg: > >>> MachinePipeliner) > >>> > >>> > >>> On 2017-01-04 18:10, Mehdi Amini wrote: > >>>>> On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev > >>>>> <llvm-dev at lists.llvm.org> wrote: > >>>>> I see the BackendUtil.c...

Hi paulr, Thank you for your response :) Hi Krzysztof, This is really helpful! Thank you for your guidance!! I would like to trace the Hexagon's llvm implementation. I am very interested on how Hexagon implement instruction pattern matching, instruction scheduling, and register allocation, could you give me some suggestions or reading lists to help me understand Hexagon's llvm