search for: machinemodulepasses

Displaying 20 results from an estimated 49 matches for "machinemodulepasses".

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2016 Jan 22
8
[GlobalISel][RFC] Thoughts on MachineModulePass
Hi, In the initial thread of the proposal for GlobalISel, I have mentioned that it may be interesting to have a kind of MachineModulePass. Marcello mentioned this would be useful for their current pipeline. I am interested in knowing: 1. If anyone else is interested for such concept? 2. What kind of information should we make accessible in an hypothetical MachineModule? I.e., how do you plan to
2016 Jan 25
2
[GlobalISel][RFC] Thoughts on MachineModulePass
...to use the MachineModulePass so that we make the right design decisions for the MachineModule feeding those passes? we are building a toolchain for real-time systems, including optimizations and analyses that deal with the machine-level code of entire real-time applications. we have implemented MachineModulePasses based on LLVM 3.4 (see the patmos-llvm repository of T-CREST). it is clearly not a final solution for wide-spread use, but it works with a few limitations. for instance, it is difficult to preserve analysis information and access it in a machine module pass. similarly, it is rather difficult to...
2016 Mar 20
2
[GSoC 2016] Need more info on Add a MachineModulePass
On 3/18/16 12:33 PM, Quentin Colombet via llvm-dev wrote: > Hi Vivek, > >> On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello, >> >> Probably this may be too late to start thinking about this project >> but I think this is particularly useful
2016 Jul 17
6
RFC: Enabling Module passes post-ISel
Hi, [Apologies to those receiving this mail twice - used the old list address by accident] In LLVM it is currently not possible to write a Module-level pass (a pass that modifies or analyzes multiple MachineFunctions) after DAG formation. This inhibits some optimizations[1] and is something I'd like to see changed. The problem is that in the backend, we emit a function at a time, from DAG
2016 Mar 16
3
[GSoC 2016] Need more info on Add a MachineModulePass
Hello, Probably this may be too late to start thinking about this project but I think this is particularly useful feature for LLVM. A quick use I can think of this is Implementing Inter-procedural Register Allocation ( for Research purpose ). I have start looking at the code for MachineFunctionPass, I think currently MachineModule class is not available ( the project work will include that ) but
2016 May 11
4
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "llvm-dev" <llvm-dev at lists.llvm.org>, "Tim Amini Golling" <mehdi.amini at apple.com>, "Hal Finkel" <hfinkel at anl.gov> > Cc: "Quentin Colombet" <qcolombet
2016 May 10
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Hello LLVM Community, Sorry for delay as I was busy in final exams. I am Vivek from India. Thanks for choosing my proposal for Interprocedural Register Allocation (IPRA) in LLVM. Mehdi Amini and Hal Finkel will be mentoring me for this project. IPRA can reduce code size and runtime of programs by allocating register across the module and procedure boundaries. I have identified some old but
2016 Mar 18
2
[GSoC 2016] Need more info on Add a MachineModulePass
*Vivek Pandya* On Fri, Mar 18, 2016 at 10:03 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Vivek, > > On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hello, > > Probably this may be too late to start thinking about this project but I > think this is particularly useful feature for LLVM. >
2016 Mar 08
3
Deleting function IR after codegen
> On Mar 8, 2016, at 11:50 AM, Eric Christopher <echristo at gmail.com> wrote: > > > > > I could attach a patch, but first i’d really like to know if anyone is fundamentally opposed to this. > > > Not necessarily. I think that any information that isn't being serialized in MI right now for a function could be as well. Definitely something for GlobalISel
2016 Mar 23
0
GSOC project inquiry.
Hi, I am Om Shivom and i am interested in adding a new pass in llvm in gsoc. I stumbled upon adding the MachineModulePass on the Open projects list ( http://llvm.org/OpenProjects.html#machinemodulepass ). Can someone help me understand the project properly or point to sources where i can get help from? Regards. -------------- next part -------------- An HTML attachment was scrubbed... URL:
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya* On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> >> >>
2016 Jan 29
1
MachineModule pass
Hello everyone, As I mentioned in my previous posts,I am using a machinefunction pass to find all the loops in the program and do some analysis on them. I have completed my pass now and it works correctly. but the only issue is that,I have noticed that if I have two functions in my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop
2016 Jul 19
4
RFC: Enabling Module passes post-ISel
...A among others depends on seeing the IR at query time. We'd need to work out a way of providing alias analysis with no IR present. I don't think that is feasible for the near future. So my suggestion is that we go with Matthias' idea - do the small amount of refactoring needed to allow MachineModulePasses on an opt-in basis. The knobs to enable that opt-in might need some more bikeshedding. Cheers, James On Tue, 19 Jul 2016 at 08:21 Justin Bogner <mail at justinbogner.com> wrote: > James Molloy via llvm-dev <llvm-dev at lists.llvm.org> writes: > > In LLVM it is currently not...
2016 May 15
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 15, 2016, at 12:43 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > Vivek Pandya > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote: > >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: >>
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya* On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Mehdi Amini" <mehdi.amini at apple.com> > *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" < > qcolombet at
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya* On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> >> ------------------------------ >> >>
2016 Aug 26
10
[RFC] Interprocedural MIR-level outlining pass
...into account. ii. Simple parameter passing. iii. Similar function outlining-- eg, noticing that two outlining candidates are similar and can be merged into one function with some control flow. ================================ Code ================================ Note: This code requires MachineModulePasses * Main pass: https://github.com/ornata/llvm/blob/master/lib/CodeGen/MachineOutliner.h * Suffix tree: https://github.com/ornata/llvm/blob/master/include/llvm/ADT/SuffixTree.h * TerminatedString and TerminatedStringList: https://github.com/ornata/llvm/blob/master/include/llvm/ADT/TerminatedString....
2016 May 18
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 18, 2016, at 11:00 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > Vivek Pandya > > > On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at
2016 May 24
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Hello, I have written following code to check each register if it is used by machineFunction or not : MachineRegisterInfo *MRI = &MF.getRegInfo(); TargetRegisterInfo *TRI = (TargetRegisterInfo *)MF.getSubtarget().getRegisterInfo(); const TargetMachine &TM = MF.getTarget(); const MCRegisterInfo *MCRI = TM.getMCRegisterInfo(); DEBUG(dbgs() << "Function Name : " <<
2013 Jun 10
1
[LLVMdev] Whole program alias analysis in backend
Hi, On 06/10/2013 09:13 AM, Jonas Wagner wrote: > Hi, > > I know that backend processes one function at a time, > is it somehow possible to do there a whole program analysis, > or could you give me some guidelines? > > The backend introduces a MachineFunctionPass, from which point on it is only possible to run FunctionPasses, otherwise the machine functions