search for: machinemodul

Displaying 20 results from an estimated 42 matches for "machinemodul".

Did you mean: machinemodule
2016 Mar 18
2
[GSoC 2016] Need more info on Add a MachineModulePass
...t but I > think this is particularly useful feature for LLVM. > > > +1. I’d like to use something this feature in GlobalISel. The idea is that > has as soon as we lowered the LLVM IR of the whole module to MachineInstr, > the LLVM IR should be deallocable. > In other words, the MachineModule/MachineFunctions should contain enough > information such that we do not have to keep the LLVM IR around. > > One of the main challenge is about alias analysis information that are > tight with LLVM IR, but may be used in MachineFunctionPass. > > A quick use I can think of this i...
2016 Jan 29
1
MachineModule pass
...my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop per each function. whereas the correct result is to find one loop at depth 1 and the other one at depth 2 as an inner loop. In order to get this result, I am trying to use write a MachineModule Pass, but I can't seem to find any MachineModule.h in codegen. Right now, is this even possible to write a machinemodule pass? If not what other options do I have to get the results I need. Thank you, Fami -------------- next part -------------- An HTML attachment was scrubbed... URL: <http...
2016 Mar 16
3
[GSoC 2016] Need more info on Add a MachineModulePass
...may be too late to start thinking about this project but I think this is particularly useful feature for LLVM. A quick use I can think of this is Implementing Inter-procedural Register Allocation ( for Research purpose ). I have start looking at the code for MachineFunctionPass, I think currently MachineModule class is not available ( the project work will include that ) but trying to find out required details to first create a MachineModule class which holds references to required information. I am also trying to figure out what are the things should compose MachineModule class ( some sort of analogy w...
2016 Jan 22
8
[GlobalISel][RFC] Thoughts on MachineModulePass
Hi, In the initial thread of the proposal for GlobalISel, I have mentioned that it may be interesting to have a kind of MachineModulePass. Marcello mentioned this would be useful for their current pipeline. I am interested in knowing: 1. If anyone else is interested for such concept? 2. What kind of information should we make accessible in an hypothetical MachineModule? I.e., how do you plan to use the MachineModulePass so that...
2016 Mar 21
1
[GSoC 2016] Adding MachineModule pass to LLVM
Hello Community, I have submitted my draft proposal for this project on the summer of code web site and shared it with the community. Please take a look at it and suggest/ comment some modifications. I have already done some study on the relevant code. I will still do some more before the final submission but this is more of designing challenge please help ! Sincerely, *Vivek Pandya*
2016 Mar 23
0
[GSoC 2016] Adding MachineModule pass to LLVM
Hello Ethan, > Hi Vivek, > > I've reviewed your MachineModulePass proposal and in general, I like > what I'm seeing. A few suggestions on how you can make it stronger: > > 1. Please go into more specific detail on your prior work with LLVM. > Specifically: > 1. Which optimizations and passes have you implemented in your >...
2016 Jan 25
2
[GlobalISel][RFC] Thoughts on MachineModulePass
Hi Quentin, > On 22 Jan 2016, at 15:16, Quentin Colombet <qcolombet at apple.com> wrote: > 1. If anyone else is interested for such concept? yes, we are! (https://github.com/t-crest) > 2. What kind of information should we make accessible in an hypothetical MachineModule? I.e., how do you plan to use the MachineModulePass so that we make the right design decisions for the MachineModule feeding those passes? we are building a toolchain for real-time systems, including optimizations and analyses that deal with the machine-level code of entire real-time applicatio...
2018 Sep 22
3
Quick question: How to BuildMI mov64mi32 arbitrary MMB address to memory
...LLVM, but I assume this is the route I should take? Pairing each trampoline BB to a symbol should make it visible and this MOVQ instruction I want possible? With that approach, my questions are: Do I need to make these symbols for the trampoline BBs as an IR opt pass, can I get away with it using a MachineModule Pass to add the trampolines per module (file) (so far I have only created BasicBlock, MachineBasicBlock, and MachineFunction passes)?? Do I need to make a separate custom section for these trampolines symbols, or can I just add them to the .text section? Thanks again for your reply. Sincerely, K...
2016 Mar 20
2
[GSoC 2016] Need more info on Add a MachineModulePass
...>> but I think this is particularly useful feature for LLVM. > > +1. I’d like to use something this feature in GlobalISel. The idea is > that has as soon as we lowered the LLVM IR of the whole module to > MachineInstr, the LLVM IR should be deallocable. > In other words, the MachineModule/MachineFunctions should contain > enough information such that we do not have to keep the LLVM IR around. I think this is a separate issue from having a MachineModulePass. My goal in having a MachineModulePass is to be able to do inter-procedural analysis and transformation on a program aft...
2016 May 11
4
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...e commands? > In terms of scoping the project for the summer, I definitely recommend that you focus on (1) first. If you finish that, we can certainly move on to other things. I'll add +1 here, but I already wrote the same thing on IRC when discussing with Vivek. True IPRA without a proper MachineModule infrastructure won't be doable in my opinion (even with such infrastructure, it may not be trivial in LLVM in general). > Regarding link time, note that any such a design would likely look much different than in David Wall's paper however, because our LTO re-codegens everything anyway....
2016 Mar 08
3
Deleting function IR after codegen
...o know if anyone is fundamentally opposed to this. > > > Not necessarily. I think that any information that isn't being serialized in MI right now for a function could be as well. Definitely something for GlobalISel to keep in mind. +1. That’s basically where I would like to go with MachineModule/MachineModulePass. http://lists.llvm.org/pipermail/llvm-dev/2016-January/094426.html Cheers, -Quentin > > I should note, a couple of issues have come up in the prototype. > - llvm::getDISubprogram was walking the function body to find the subprogram. This is trivial to fix as function...
2009 Mar 26
1
[LLVMdev] how to get the InvodInst 's Operand Name?
Hi Duncan, >>I don't get it. Sorry my bad English! hehe. >>What has this got to do with determining the >>names "@__cxa_throw" and "@_ZTi"? Record the Information into the MachineModule Info, so in Dwarfwriter or SjLjWriter(my sjlj-eh name) can build the except table correctly! 2009/3/26 Duncan Sands <baldrick at free.fr>: > Hi zhangzw, > >> >> Why do you want the names anyway? >> >> because i 'am working on llvm to support sjlj-eh for...
2016 May 15
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...t;> In terms of scoping the project for the summer, I definitely recommend that you focus on (1) first. If you finish that, we can certainly move on to other things. > > I'll add +1 here, but I already wrote the same thing on IRC when discussing with Vivek. True IPRA without a proper MachineModule infrastructure won't be doable in my opinion (even with such infrastructure, it may not be trivial in LLVM in general). > >> Regarding link time, note that any such a design would likely look much different than in David Wall's paper however, because our LTO re-codegens everythin...
2013 Jun 10
1
[LLVMdev] Whole program alias analysis in backend
...ackend introduces a MachineFunctionPass, from which point on it is only possible to run FunctionPasses, otherwise the machine functions get screwed. For our project, we also want do to whole-program analyses. I managed to patch the PassManager, MachineFunctionPass and others to work with a new MachineModule pass I introduced in our copy of LLVM. Now we can run module passes in the backend, and have proper pass dependencies between any combination of function passes and module passes (I haven't tested my changes with any kind of basic block- or loop-passes). However, this was not an easy task....
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...the summer, I definitely recommend >> that you focus on (1) first. If you finish that, we can certainly move on >> to other things. >> >> >> I'll add +1 here, but I already wrote the same thing on IRC when >> discussing with Vivek. True IPRA without a proper MachineModule >> infrastructure won't be doable in my opinion (even with such >> infrastructure, it may not be trivial in LLVM in general). >> >> Regarding link time, note that any such a design would likely look much >> different than in David Wall's paper however, because...
2016 May 12
2
Deleting function IR after codegen
...y. I think that any information that isn't being > > > serialized in MI right now for a function could be as well. > > > Definitely something for GlobalISel to keep in mind. > > > > > +1. > > > That’s basically where I would like to go with > > MachineModule/MachineModulePass. > > > http://lists.llvm.org/pipermail/llvm-dev/2016-January/094426.html > > > Cheers, > > > -Quentin > > > > > I should note, a couple of issues have come up in the > > > > prototype. > > > > > > &g...
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...? > In terms of scoping the project for the summer, I definitely recommend that you focus on (1) first. If you finish that, we can certainly move on to other things. > > I'll add +1 here, but I already wrote the same thing on IRC when discussing with Vivek. True IPRA without a proper MachineModule infrastructure won't be doable in my opinion (even with such infrastructure, it may not be trivial in LLVM in general). > > Regarding link time, note that any such a design would likely look much different than in David Wall's paper however, because our LTO re-codegens everything an...
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...? > In terms of scoping the project for the summer, I definitely recommend that you focus on (1) first. If you finish that, we can certainly move on to other things. > > I'll add +1 here, but I already wrote the same thing on IRC when discussing with Vivek. True IPRA without a proper MachineModule infrastructure won't be doable in my opinion (even with such infrastructure, it may not be trivial in LLVM in general). > > Regarding link time, note that any such a design would likely look much different than in David Wall's paper however, because our LTO re-codegens everything an...
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...y recommend >>> that you focus on (1) first. If you finish that, we can certainly move on >>> to other things. >>> >>> >>> I'll add +1 here, but I already wrote the same thing on IRC when >>> discussing with Vivek. True IPRA without a proper MachineModule >>> infrastructure won't be doable in my opinion (even with such >>> infrastructure, it may not be trivial in LLVM in general). >>> >>> Regarding link time, note that any such a design would likely look much >>> different than in David Wall's pa...
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> > > > I'll add +1 here, but I already wrote the same thing on > > > > > > > > IRC > > > > > > > > when > > > > > > > > discussing with Vivek. True IPRA without a proper > > > > > > > > MachineModule > > > > > > > > infrastructure won't be doable in my opinion (even with > > > > > > > > such > > > > > > > > infrastructure, it may not be trivial in LLVM in > > > > > > > > general). > > >...