Displaying 6 results from an estimated 6 matches for "machineloops".
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machineloop
2011 Jul 28
1
[LLVMdev] Is MachineLoop Simplify Form?
Is there any reason that we don't have isLoopSimplifyForm method in LoopBase? Can I move it there?
-Kuba
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2019 May 10
2
[Pipeliner] MachinePipeliner TargetInstrInfo hooks need more information?
Hello,
I'm working on integrating the MachinePipeliner.cpp pass into our VLIW
backend, and so far we've managed to get it working with some nice
speedups.
Unlike Hexagon however, our backend doesn't generate hardware loop
instructions and so all our loops are a combination of induction
variables, comparisons and branches. So when it came to implementing
reduceLoopCount for our
2010 Mar 09
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Thank you, Nick.
Yes, I have add getAnalysisUsage.
As I know, some CFG is irreducible.
At this time, Dominator Tree can not find
some backedge. Is it means some MachineLoop is
not be found?
dominatorTree.jpg is a previous exmaple.
best regards!
renkun
--- 10年3月9日,周二, Nick Lewycky <nicholas at mxc.ca> 写道:
> 发件人: Nick Lewycky <nicholas at mxc.ca>
> 主题: Re: [LLVMdev] Find
2010 Mar 09
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Hi:
I want to do some optimization on MachineLoop.
So I want to get MachineLoopInfo from MachineFunction.
I reference MachineLICM.cpp.
So I try to write a pass in Target/mytarget directory.
I find there is Error.
llvm/include/llvm/PassAnalysisSupport.h:198: AnalysisType& llvm::Pass::getAnalysisID(const llvm::PassInfo*) const [with AnalysisType = llvm::MachineLoopInfo]: Assertion
2018 Nov 10
2
[RFC] Tablegen-erated GlobalISel Combine Rules
Thanks David!
> On Nov 9, 2018, at 08:36, David Greene <dag at cray.com> wrote:
>
> Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org> writes:
>
>> I've been working on the GlobalISel combiner recently and I'd like to
>> share the plan for how Combine Rules will be defined in GlobalISel and
>> solicit feedback on it.
>
> This is
2018 Nov 15
2
[RFC] Tablegen-erated GlobalISel Combine Rules
> On Nov 13, 2018, at 08:01, David Greene <dag at cray.com> wrote:
>
> Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org> writes:
>
>> That's an interesting idea. Certainly tablegenerating InstCombine
>> ought to be possible and sharing code sounds like it ought to be
>> doable. MIR and IR are pretty similar especially after IRTranslator