search for: machineir

...9;s > a reason *not* to do this. > > Here's some more context: > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150518/278031.html <http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150518/278031.html> I have no objections, though I think lib/MachineIR would make a prettier bikeshed ;-) —Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150526/fd523047/attachment.html>

...w way of writing algorithms that are generic over different types of CFG. What is this? ============= This series of patches introduces a set of classes and templates for: 1. Working on basic blocks and values generically, in particular with the same algorithm implementation on both LLVM IR and MachineIR (in SSA form), and 2. Doing so using type erasure, i.e. the bulk of the algorithm you're writing doesn't have to be a template (at the cost of using some virtual methods). The second point is achieved by a) having algorithms refer to blocks and values using CfgBlockRef and CfgValueRe...

Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...

Dear LLVM developers, My goal is to write LLVM Machine IR (MIR) passes to analyze the assembly source code. But it seems I need to find a way to translate the handwritten assembly code into MIR format first. Is there any materials, or any modules in LLVM source code, that can help to translate assembly code into LLVM MIR for analysis? Or is there any easier ways to analyze assembly code in MIR

...o MIR format first. > > > > Is there any materials, or any modules in LLVM source code, that can > help to translate assembly code into LLVM MIR for analysis? > > > > Or is there any easier ways to analyze assembly code in MIR passes > without translating it? > > MachineIR is designed for code generation, not for general assembly > representation. MIR is even not necessarily able to represent all > assembly instructions that a target's hardware supports. The > disassembler produces MCInsts, and if you wanted to go from there back > to MachineIR, you...

...CFG. >> >> >> What is this? >> ============= >> This series of patches introduces a set of classes and templates for: >> >> 1. Working on basic blocks and values generically, in particular with >> the same algorithm implementation on both LLVM IR and MachineIR (in SSA >> form), and >> >> 2. Doing so using type erasure, i.e. the bulk of the algorithm you're >> writing doesn't have to be a template (at the cost of using some virtual >> methods). >> >> The second point is achieved by >> >> a) hav...

....llvm.org; > llvm-dev <llvm-dev at lists.llvm.org> > Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? > > > Andrew Kaylor wrote: > >In general, the current "strict FP" handling stops at instruction > >selection. At the MachineIR level we don't currently have a mechanism > >to prevent inappropriate optimizations based on floating point > >constraints, or indeed to convey such constraints to the backend. > >Implicit register use modeling may provide some restriction on some > >architec...

...any materials, or any modules in LLVM source code, that can >>> help to translate assembly code into LLVM MIR for analysis? >>> > >>> > Or is there any easier ways to analyze assembly code in MIR passes >>> without translating it? >>> >>> MachineIR is designed for code generation, not for general assembly >>> representation. MIR is even not necessarily able to represent all >>> assembly instructions that a target's hardware supports. The >>> disassembler produces MCInsts, and if you wanted to go from there back...

...;llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? > > Andrew Kaylor wrote: > > >In general, the current "strict FP" handling stops at instruction > >selection. At the MachineIR level we don't currently have a mechanism > >to prevent inappropriate optimizations based on floating point > >constraints, or indeed to convey such constraints to the backend. > >Implicit register use modeling may provide some restriction on some > >architectures, but t...

...ow I'm representing unique instructions with nondescript numeric symbols, like "i28" for the 28th instruction; but it would be nice to give the reader something more helpful like "i28_MOV32ri64". MachineInstr doesn't have a getName() function like many other LLVM IR/MachineIR objects; is there anything roughly equivalent to this? I'm already using MachineInstr::print() for debugging output, but it's far too verbose for this purpose. I thought about trying to parse the opcode mnemonic out of the print() output, until I realized just how nasty that would be (n...

...gt;> >>> Here's some more context: >>> >>> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150518/278031.html <http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150518/278031.html> >> I have no objections, though I think lib/MachineIR would make a prettier bikeshed ;-) > > +1. Codegen should also be renamed to something else that starts with “Machine” as well. > > -Chris > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.u...

...mail.com; wei.ding2 at amd.com; cfe-dev at lists.llvm.org; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...

...lists.llvm.org>; llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...

...mail.com; wei.ding2 at amd.com; cfe-dev at lists.llvm.org; llvm-dev <llvm-dev at lists.llvm.org> *Subject:* Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...

...he outliner technology forward and I’d like to avoid that if at > all possible. > It isn't clear to me that implementing it at the MachineLevel was the right trade-off in the first place. I'm not sure a full comparative study was performed and discussed upstream at the time where the MachineIR outliner was implemented? If so it wouldn't be fair to ask this to River now. -- Mehdi -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170725/fcb0e1a0/attachment.html>

...s a new PM equivalent. My knowledge on Codegen is close to being non-existent, but as far as I see there is no New-PM equivalent for CodeGen passes/analyses at all. And as Chandler and others told me, NewPM CodeGen work not yet done includes fleshing out a "new-style" IRUnit support for MachineIR (Pass/Analysis Managers for those). You can surely convert some Codegen FunctionPass'es into NewPM, but you wont be able to create a fully operational CodeGen pipeline w/o a MachineIR. (this is not to discourage your effort on doing the port though :) ... > My question is what would be t...

...gmail.com; wei.ding2 at amd.com; cfe-dev at lists.llvm.org; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...

...rely on debug info, because some optimizations will (correctly) erase it. The long version: When Clang generates IR with debug info, one thing it does is attach a source location to most IR instructions. This source location (at least in principle) is carried through optimizations, SelectionDAG, MachineIR, assembler source, and ultimately ends up in the "line table" in the object file. The line table describes a mapping from the virtual addresses of instructions to source locations, which is very useful to debuggers and other tools. Not all IR instructions have a source location attached...

...nting it at the MachineLevel was the > right trade-off in the first place. > > > Fair enough. it has the advantage of not rely on heuristic for its cost > model though. > > I'm not sure a full comparative study was performed and discussed upstream > at the time where the MachineIR outliner was implemented? If so it wouldn't > be fair to ask this to River now. > > > I am not asking that :). > OK great :) -- Mehdi 2017-07-26 9:31 GMT-07:00 Quentin Colombet <qcolombet at apple.com>: > > On Jul 25, 2017, at 10:36 PM, Mehdi AMINI <joker.e...

...mail.com; wei.ding2 at amd.com; cfe-dev at lists.llvm.org; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported? Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some >architectures, but this is definitely la...