search for: machineinstrbundle

Hi, > Has anyone attempted the port of LLVM to a VLIW architecture? Is there > any publication about it? I have developed a derivation of MachineInstr class, called MachineInstrBundle, which is essnetially a VLIW-style machine instruction which can store any MI on each "slot". After the scheduling phase has grouped MIs in bundles, it has to call MIB->pack() method, which takes operands from the MIs in the "slots" and transfers them to the superinstruction....

Has anyone attempted the port of LLVM to a VLIW architecture? Is there any publication about it? TIA -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

Hi all, here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided as an example. Ma...

...library. These are: - MachineBasicBlock - MachineBlockFrequencyInfo - MachineBlockPlacement - MachineBranchProbabilityInfo - MachineCodeEmitter - MachineCopyPropagation - MachineCSE - MachineDominators - MachineFunctionAnalysis - MachineFunction - MachineFunctionPass - MachineFunctionPrinterPass - MachineInstrBundle - MachineInstr - MachineLICM - MachineLoopInfo - MachineModuleInfo - MachineModuleInfoImpls - MachinePassRegistry - MachinePostDominators - MachineRegisterInfo - MachineScheduler - MachineSink - MachineSSAUpdater - MachineTraceMetrics - MachineVerifier Are there any files in this list that should...

...FrequencyInfo > - MachineBlockPlacement > - MachineBranchProbabilityInfo > - MachineCodeEmitter > - MachineCopyPropagation > - MachineCSE > - MachineDominators > - MachineFunctionAnalysis > - MachineFunction > - MachineFunctionPass > - MachineFunctionPrinterPass > - MachineInstrBundle > - MachineInstr > - MachineLICM > - MachineLoopInfo > - MachineModuleInfo > - MachineModuleInfoImpls > - MachinePassRegistry > - MachinePostDominators > - MachineRegisterInfo > - MachineScheduler > - MachineSink > - MachineSSAUpdater > - MachineTraceMetrics >...

...:llvmdev-bounces at cs.uiuc.edu] Im Auftrag von Carlos Sánchez de La Lama Gesendet: Donnerstag, 6. Oktober 2011 13:14 An: LLVM Dev Betreff: Re: [LLVMdev] VLIW Ports Hi all, here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided as an example. Ma...

...sure that CCR is never live. I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of cmp instruction so I might need a lot of pseudos. That's what led me to wonder whether MachineInstrBundles might be a neater solution but I wasn't sure whether they were really intended, or suitable, for this purpose. Steve On 3 Jun 2013, at 17:30, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 3, 2013, at 6:05 AM, Steve Montgomery <stephen.montgomery3 at btinternet...

...the information about registers used > and defined, and it would have a link to the actual instructions that > define it. BTW did anyone seriously consider the Carlos' proposal? The inheritance idea has its merits as it can hide several behaviors/semantics behind the "mother" MachineInstrBundle class, as far as I've understood. http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/043798.html -- --Pekka

...Auftrag von Carlos Sánchez de La Lama > Gesendet: Donnerstag, 6. Oktober 2011 13:14 > An: LLVM Dev > Betreff: Re: [LLVMdev] VLIW Ports > > Hi all, > > here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. > > Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided as an ex...

...ver live. > > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of cmp instruction so I might need a lot of pseudos. > > That's what led me to wonder whether MachineInstrBundles might be a neater solution but I wasn't sure whether they were really intended, or suitable, for this purpose. That might be possible, at least the register allocator understands bundles. Passes before register allocation are not bundle aware, including the MI scheduler. You may be able to f...

...Auftrag von Carlos Sánchez de La Lama > Gesendet: Donnerstag, 6. Oktober 2011 13:14 > An: LLVM Dev > Betreff: Re: [LLVMdev] VLIW Ports > > Hi all, > > here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. > > Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided as an ex...

...de La Lama >> Gesendet: Donnerstag, 6. Oktober 2011 13:14 >> An: LLVM Dev >> Betreff: Re: [LLVMdev] VLIW Ports >> >> Hi all, >> >> here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. >> >> Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided...

I just signed up to this mailing list so I don't have the original email with the proposal to reply to. I got the text forwarded to me though, and here are my thoughts on it: - The requirement that it should be easy for a pass to be oblivious to bundles isn't well defined. If this means that a pass should be able to run as if the bundles weren't present, then such a pass can easily

...de La Lama >> Gesendet: Donnerstag, 6. Oktober 2011 13:14 >> An: LLVM Dev >> Betreff: Re: [LLVMdev] VLIW Ports >> >> Hi all, >> >> here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. >> >> Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided...

...ndet: Donnerstag, 6. Oktober 2011 13:14 >>> An: LLVM Dev >>> Betreff: Re: [LLVMdev] VLIW Ports >>> >>> Hi all, >>> >>> here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. >>> >>> Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just p...

...rstag, 6. Oktober 2011 13:14 > >> An: LLVM Dev > >> Betreff: Re: [LLVMdev] VLIW Ports > >> > >> Hi all, > >> > >> here is the current (unfinished) version of the VLIW support I mentioned. > It is a patch over svn rev 141176. It includes the MachineInstrBundle class, > and small required changes in a couple of outside LLVM files. > >> > >> Also includes a modification to Mips target to simulate a 2-wide VLIW > MIPS. The scheduler is really silly, I did not want to implement a > scheduler, just the bundle class, and the test sc...

...z de La Lama >> Gesendet: Donnerstag, 6. Oktober 2011 13:14 >> An: LLVM Dev >> Betreff: Re: [LLVMdev] VLIW Ports >> >> Hi all, >> >> here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. >> >> Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just provided a...

...rstag, 6. Oktober 2011 13:14 > >> An: LLVM Dev > >> Betreff: Re: [LLVMdev] VLIW Ports > >> > >> Hi all, > >> > >> here is the current (unfinished) version of the VLIW support I mentioned. > It is a patch over svn rev 141176. It includes the MachineInstrBundle class, > and small required changes in a couple of outside LLVM files. > >> > >> Also includes a modification to Mips target to simulate a 2-wide VLIW > MIPS. The scheduler is really silly, I did not want to implement a > scheduler, just the bundle class, and the test sc...

...ch for bundle start / end like all the code in the backend that skip over DBG_VALUE). 4. The representation should make it easy for new code to be oblivious of bundles. That is, MI passes should not have to check whether something is a bundle. Given the above, we can rule out a new class (e.g. MachineInstrBundle) right away. We don't want MachineBasic block to keep a list of MachineInstrBundles since it will require massive amount of code change. So what are the choices? Bundle Representation 1. A nested MachineInstr: This is the most natural (meaning it looks most like the real HW bundle) repr...

...ndet: Donnerstag, 6. Oktober 2011 13:14 >>> An: LLVM Dev >>> Betreff: Re: [LLVMdev] VLIW Ports >>> >>> Hi all, >>> >>> here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. >>> >>> Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and the test scheduler is just p...