search for: machinecopypropag

> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: > > *** Bad machine code: Multiple connected components in live interval *** > - function: utils_la_suite_matmul_ref > - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[38...

On 9/26/2017 6:11 PM, Matthias Braun wrote: > >> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi all, >> >> Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: >> >> *** Bad machine code: Multiple connected components in live interval *** >> - function: utils_la_suite_matmul_ref >> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[...

...t; On 9/26/2017 6:11 PM, Matthias Braun wrote: >>> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>> >>> Hi all, >>> >>> Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: >>> >>> *** Bad machine code: Multiple connected components in live interval *** >>> - function: utils_la_suite_matmul_ref >>> - interval: %vreg77 [192r,208B...

Hi all, Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: *** Bad machine code: Multiple connected components in live interval *** - function: utils_la_suite_matmul_ref - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 1...

...out of the available registers. So I gave up and tried createVirtualRegister(): MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); const TargetRegisterClass *RC = &LASER::GNPRegsRegClass; unsigned Reg = RegInfo.createVirtualRegister(RC); But then I get the following error: MachineCopyPropagation.cpp:267: void anonymous}::MachineCopyPropagation::CopyPropagateBlock(llvm::MachineBasicBlock&): Assertion `!TargetRegisterInfo::isVirtualRegister(Reg) && "MachineCopyPropagation should be run after register allocation!"' failed. How can I solve my problem of getting...

Hi, I have the following code: %a1<def> = COPY %a0<kill> ... %a0h<def> = COPY %a1l , as input to MachineCopyPropagation. The second copy is illegally erased! This is wrong, because it is the low part of a1 that is copied to the high part of a0. At a first glance, it seems that if (!ReservedRegs.test(Def) && (!ReservedRegs.test(Src) || NoInterveningSideEffect(CopyMI, MI)) && (SrcS...

...ff Berry via llvm-dev >>>> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >>>> >>>> Hi all, >>>> >>>> Mikael reported a machine verification failure in his out-of-tree >>>> target with the MachineCopyPropagation changes to forward registers >>>> (which is currently reverted).  The verification in question is: >>>> >>>> *** Bad machine code: Multiple connected components in live interval *** >>>> - function:    utils_la_suite_matmul_ref >>>>...

...7, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >>>>> >>>>> Hi all, >>>>> >>>>> Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: >>>>> >>>>> *** Bad machine code: Multiple connected components in live interval *** >>>>> - function: utils_la_suite_matmul_ref >>>>> -...

Hi, anyone know anything about copy propagation? Matthias, I see this was your code originally? Was there some assumptions you made? I'm hitting an assertion in MachineCopyPropagation::isNopCopy: if (Src == PreviousSrc) { assert(Def == PreviousDef); return true; } This code compares two COPY instruction to see whether they are effectively "the same". The assert assumes that, if the sources are the same register then the destinations must be as well. My i...

Forgive me if these questions are naive or if I'm misunderstanding something. I'm certainly very interested in seeing the MachineCopyPropagation patch finally land and stick. 1. Wouldn't function live-ins and reserved registers have started life as physical registers already? For example, wouldn't a live-in be a copy from a physical register to a virtual one allowing the flag to be set correctly on the def? A reserved register...

I need to use ‘createVirtualRegister’ for a specific case in my ‘eliminateFrameIndex’ function implementation. However, whenever that code is executed, I get the assertion "MachineCopyPropagation should be run after register allocation!” at a later stage. I have seen that at least a couple of backend implementations (including ARM Thumb) create virtual registers in ‘eliminatedFrameIndex’. What am I missing?, is there something that I need to set for virtual registers to be allowed af...

...y (and not be caught be verification) would be if a post-RA pass was already renaming a register definition from a previously virtual register to a previously non-virtual register, which would arguably be a bug already. We have encountered several potential uses for this bit. For example, the MachineCopyPropagation changes I have been working on to forward register COPYs would likely be greatly simplified if this bit were available. Other passes, like AArch64LoadStoreOptimizer, which run post-RA so as not to overly-restrict the register allocator, could be made to catch more cases if renaming of loa...

...m tempted to think no, we don’t, but I don’t know the use cases. > What post-RA passes with want to run with virtual regs? > > The immediate one that precipitated this mail was PrologEpilogInserter. > However currently the only other pass we have disabled in WebAssemblyTargetMachine is MachineCopyPropagation. > Several passes (post-RA MachineLICM, StackSlotColoring) already only run if RA runs. > Everything else is running today. Currently that's ShrinkWrap, BranchFolder, ExpandPostRAPseudos, PostRAScheduler, GCMachineCodeAnalysis, MachineBlockPlacement, FuncletLayout, and StackMapLivene...

...(ordered and categorized according to how they appear in lib/CodeGen/Passes.cpp): OptimizedRegAlloc: (run only if there is a RegAllocPass, which is not true for wasm) StackSlotColoring PostRAMachineLICM ShrinkWrap PrologEpilogInserter Machine late optimization: BranchFolderPass TailDuplicate MachineCopyPropagation PostRAScheduler ExpandPostRAPseudos ImplicitNullChecks (optional) PostMachineScheduler or PostRAScheduler GC: GCMachineCodeAnalysis GC info printer Block Placement: MachineBlockPlacement MachineBlockPlacementStats FuncletLayout StackMapLiveness LiveDebugValues All of the pre-regalloc pas...

...into the problem yet, but I'm starting from the assumption that we'll be moving only the modules that start with 'Machine' into the new library. These are: - MachineBasicBlock - MachineBlockFrequencyInfo - MachineBlockPlacement - MachineBranchProbabilityInfo - MachineCodeEmitter - MachineCopyPropagation - MachineCSE - MachineDominators - MachineFunctionAnalysis - MachineFunction - MachineFunctionPass - MachineFunctionPrinterPass - MachineInstrBundle - MachineInstr - MachineLICM - MachineLoopInfo - MachineModuleInfo - MachineModuleInfoImpls - MachinePassRegistry - MachinePostDominators - Machi...

...mplex; d(complex *e, complex *h) { double f = h->c, g = h->b; i(g); e->c = g * j(f); } This was a reduction from texlive's c_cos.c. The applicable assertion failure is: Assertion failed: (Def == PreviousDef), function isNopCopy, file /home/chmeee/llvm_git/llvm/llvm/lib/CodeGen/MachineCopyPropagation.cpp, line 338. PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace. Stack dump: 0. Program arguments: /ralga/scratch/chmeee/builds/llvm/bin/llc -mtriple powerpcspe reduced.ll 1. Running pass 'Function Pass Manager' on module 'reduced.ll...

...gt; lib/CodeGen/Passes.cpp): > > OptimizedRegAlloc: (run only if there is a RegAllocPass, which is not true > for wasm) > StackSlotColoring > PostRAMachineLICM > ShrinkWrap > PrologEpilogInserter > Machine late optimization: > BranchFolderPass > TailDuplicate > MachineCopyPropagation > PostRAScheduler > ExpandPostRAPseudos > ImplicitNullChecks (optional) > PostMachineScheduler or PostRAScheduler > GC: > GCMachineCodeAnalysis > GC info printer > Block Placement: > MachineBlockPlacement > MachineBlockPlacementStats > FuncletLayout > S...

Hi All, I was looking into MachineCopyPropagationPass.ccp file in llvm, which in first look, looks likes to me doing only redundant copy elimination in same basic block. I am interested in any pass which is doing copy propogation across the basic block in a function. Let me know if any such pass exist ? Thanks, Deepali -------------- next...

> On Dec 10, 2015, at 9:39 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > ----- Original Message ----- >> From: "Quentin Colombet" <qcolombet at apple.com> >> To: "Derek Schuff" <dschuff at google.com> >> Cc: "Hal Finkel" <hfinkel at anl.gov>, llvm-dev at lists.llvm.org >> Sent: Wednesday, December

Hi, I noticed that a while ago the isSSA flag was removed from MIR, and this property is now computed. However, the deduction only checks the virtual registers (whether they are assigned to more than once). Now I have MIR tests which live after RA, so they only contain physical registers, so the parser determines they are in SSA form. These tests now fail because some of our passes can be