search for: machinecombiner

Displaying 14 results from an estimated 14 matches for "machinecombiner".

2015 Feb 04
2
[LLVMdev] Question on Machine Combiner Pass
...h Grang [mailto:mgrang at codeaurora.org] Sent: Tuesday, February 03, 2015 4:34 PM To: 'llvmdev at cs.uiuc.edu' Cc: 'ghoflehner at apple.com'; 'apazos at codeaurora.org'; mgrang at codeaurora.org Subject: Question on Machine Combiner Pass Hi, In the file lib/CodeGen/MachineCombiner.cpp I see that in the function MachineCombiner::preservesCriticalPathLen we try to determine whether the new combined instruction lengthens the critical path or not. In order to do this we compute the depth and latency for the current instruction (MUL+ADD) and the alternate instruction (MADD)....
2017 Jan 28
2
RFC: Moving DAG heuristic-based transforms to MI passes
...t; improvements in that area. For the initial change (reciprocal >> transform), any difference is limited to fast-math compilations. >> >> Any objections, suggestion, comments? >> > > Are you asking whether is okay to commit the change first and then > look at the MachineCombiner's worst-case performance in followup? In > general, I think that moving to using the MachineCombiner for these > kinds of transformations, where there are complex tradeoffs between > latency, throughput, etc., is the right direction. > > -Hal > >> >> __________...
2015 Oct 02
2
Register Spill Caused by the Reassociation pass
This conflict is with many optimizations incl. copy prop, coalescing, hoisting etc. Each could increase register pressure and with similar impact. Attempts to control the register pressure locally (within an optimization pass) tend to get hard to tune and maintain. Would it be a better way to describe eg in metadata how to undo an optimization? Optimizations that attempt to reduce pressure like
2017 Jan 27
2
RFC: Moving DAG heuristic-based transforms to MI passes
All llvm-devs, We're going to introduce the new possible implementation for such optimizations as reciprocal estimation instead of fdiv. In short it's a replacement of fdiv instruction (which is very expensive in most of CPUs) with alternative sequence of instructions which is usually cheaper but has appropriate precision (see genReciprocalDiv in lib/Target/X86/X86InstrInfo.cpp for
2016 Nov 19
2
FMA canonicalization in IR
...FMF): No, I think that we specifically don't want to canonicalize to fmuladd at the IR level at all. If the backend has the freedom to form FMAs as it sees fit, then we should delay the decision until whenever the backend finds most appropriate. Some backends, for example, form FMAs using the MachineCombiner pass which considers critical path, latency, throughputs, etc. in order to find the best fusion opportunities. We only use fmuladd when required to restrict the backend to certain choices due to source-language semantics. Thanks again, Hal > > define float @foo(float %a, float %b, float %c)...
2020 Sep 15
2
[Release-testers] [11.0.0 Release] Please help writing release notes!
...tion exploitation, especially for vector permute on LE > Scheduling enhancements > > Added MacroFusion for POWER8 > Added post-ra heuristics for POWER9 > > Target dependent passes tuning > > Updated LoopStrengthReduce to use instruction number as first priority > Enhanced MachineCombiner to expose more ILP > > Code quality and maintenance enhancements > > Enabled more machine verification passes > Added ability to parse and emit additional extended mnemonics > Numerous bug fixes > > AIX Support Improvements: > > Enabled compile and link such that a sim...
2016 Nov 20
5
FMA canonicalization in IR
...don't want to canonicalize to > > fmuladd at the IR level at all. If the backend has the freedom to > > form FMAs as it sees fit, then we should delay the decision until > > whenever the backend finds most appropriate. Some backends, for > > example, form FMAs using the MachineCombiner pass which considers > > critical path, latency, throughputs, etc. in order to find the best > > fusion opportunities. We only use fmuladd when required to restrict > > the backend to certain choices due to source-language semantics. > > I'll also add that, in general, w...
2020 Aug 25
2
[11.0.0 Release] Please help writing release notes!
Hello everyone, With the release drawing near, it would be great to get the release notes into better shape. You can see the notes from rc2 online here: https://prereleases.llvm.org/11.0.0/#rc2 The release notes are typically the first thing people look at after the release, so it's a great opportunity to highlight the work that's been done since the last release. If you can think of
2020 Oct 01
2
[Release-testers] [11.0.0 Release] Please help writing release notes!
...nhancements >> > >> > Added MacroFusion for POWER8 >> > Added post-ra heuristics for POWER9 >> > >> > Target dependent passes tuning >> > >> > Updated LoopStrengthReduce to use instruction number as first priority >> > Enhanced MachineCombiner to expose more ILP >> > >> > Code quality and maintenance enhancements >> > >> > Enabled more machine verification passes >> > Added ability to parse and emit additional extended mnemonics >> > Numerous bug fixes >> > >> > AIX...
2016 Feb 03
2
[buildSchedGraph] memory dependencies
...n faced with the task of doing this, I realized that the MachineMemOperands might do the job. I tried the following and wonder why this is not done already, perhaps as a default implementation of areMemAccessesTriviallyDisjoint(). Is it because memory operands may be missing, or is it because MachineCombiner may give the register based analysis an advantage? This is a check in the case of the *same Value*. In this case the Value is an argument, which is unsafe against others, but I am thinking it should at least be safe against itself... diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen...
2016 Nov 27
5
Extending Register Rematerialization
Hello LLVM Developers, We are working on extending currently available register rematerialization to include cases where sequence of multiple instructions is required to rematerialize a value. We had a discussion on this in community mailing list and link is here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777 >From the above discussion and studying the code we
2016 Sep 08
2
Pattern transformation between scalar and vector on IR.
Hi All, I'm tring to use RSQRT instructions on follow case for ARM (now what using is sqrt): 1.0 / sqrt(x) The RSQRT instructions(VRSQRTE/VRSQRTS) are vector type, but above operation is scalar type. So a transformation must be done(transform sqrt pattern to rsqrt). I have completed a patch for this, but I made the transformation in the backend which will leads to additional
2017 Jan 21
12
[GlobalISel] Quick Status
Hi all, Following the thread from http://lists.llvm.org/pipermail/llvm-dev/2017-January/109029.html, I am sending this email to give a status on GlobalISel progress and situation. We are pushing GlobalISel from the state of prototype to a production quality framework. We welcome help with patches, reviews, feedbacks and so on. As explained during the last developer meeting, we are aiming at
2015 Jul 29
1
[LLVMdev] Error when i am using command make -j4 command in cygwin to compile safecode
...or Release+Asserts build llvm[2]: Compiling MCStreamer.cpp for Release+Asserts build llvm[3]: Compiling PDBSymbolTypeEnum.cpp for Release+Asserts build llvm[2]: Compiling SampleProf.cpp for Release+Asserts build llvm[3]: Compiling PDBSymbolTypeFriend.cpp for Release+Asserts build llvm[2]: Compiling MachineCombiner.cpp for Release+Asserts build llvm[2]: Compiling SampleProfReader.cpp for Release+Asserts build llvm[3]: Compiling PDBSymbolTypeFunctionArg.cpp for Release+Asserts build llvm[2]: Compiling MCSubtargetInfo.cpp for Release+Asserts build llvm[3]: Compiling PDBSymbolTypeFunctionSig.cpp for Release+Asse...