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Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160505/a538aa...

...m the information avaiable. There are limitation to this as the IR is incomplete, as pointed by in paper "A compiler level intermediate representation based binary analysis and rewriting system", mentioned in a discussion here (http://stackoverflow.com/questions/6981810/translation-of-machinecode-into-llvm-ir-disassembly-reassembly-of-x86-64-x86). I am not sure whether creating scheduling DAG or some intermediate representation on top of MCInst for Hazard recognition makes sense. Is suggestion on the right approach ? Regards, Pankaj -------------- next part -------------- An HTML attachm...

...B on IR level ( working on *.bc by writing a pass) > 2. llc *.bc ( generate machine code) > 3. as -o *.s *o ( generate object file, or use gcc ) > 4. ld -o *.out *.o ( generate executable file) > > during step 2, we read *.bc code and find dummy BB and put some > meaningless machinecode, here, we cannot put some illegal machince > code, otherwise, step 3 goes to fail. Yes, you are correct -- if you want to create illegal code you need to not use system as. What you need is the ability for llc to create object files with native code directly, without using the system assemb...

...ing, 1. generate some dummy BB on IR level ( working on *.bc by writing a pass) 2. llc *.bc ( generate machine code) 3. as -o *.s *o ( generate object file, or use gcc ) 4. ld -o *.out *.o ( generate executable file) during step 2, we read *.bc code and find dummy BB and put some meaningless machinecode, here, we cannot put some illegal machince code, otherwise, step 3 goes to fail. So is it possible to do that for inserting any machine code into BB? if so, how could we chang llc? I take a look at MachineInstr.c CodeGenerator.c etc, but I still don't know how to do it. Here is a thing that...

...e: whats the best way to attach the profile info also the MachineBlocks and MachineFunctions? I was thinking of converting the ProfileInfo into a template and using it for both BasicBlocks and MachineBasicBlocks. And where is the best point to transfer this information from the bytecode CFG to the machinecode CFG? Thanks, Andi - -- ========================================================================== This email is signed, for more information see http://web.student.tuwien.ac.at/~e0325716/gpg.html -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla -...

...ject file. * --list-targets LLVMGetFirstTarget/LLVMGetNextTarget and whatever can be extracted from them * --calc Test Core.h irbuilding and possibly executionengine. Create a module with a function evaluating the specified aritmetic expression. Possibly generating machinecode and executing. anders

...related mypass.cpp file; task 3(instantiation of the pass class) should be done in LinkAllPasses.h; task 4(registration of the pass into the PassRegistry) should be done by INITIALIZE_PASS class LiveVariables : public MachineFunctionPass is a case of point. For a built-into codegen/MachineCode pass, task 1 should be done in Passes.h; task 2 should be done in the related mypass.cpp file; task 3 should be done in LLVMTargetMachine.cpp task 4 should be done by INITIALIZE_PASS class IntervalAnalylsis: public MachineFunctionPass is a case in point. I have im...

...and code quality. In a jit you do not care if the register allocation is not optimal, when you get your compiled code fast. If you want to compete with GCC, every stack spill counts! tl;dr much faster code gen (even if it costs code quality), lower memory use, more information about the generated machinecode. Regards, Joerg Bank

Hi, In the context of MachineCode custom inserter, I'm trying to enforce the mapping of virtual register to a physical one. According to the documentation https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers There are two ways: the direct one and the indirect ones. The indirect ones refer V...

...> profile info also the MachineBlocks and MachineFunctions? I was > thinking > of converting the ProfileInfo into a template and using it for both > BasicBlocks and MachineBasicBlocks. > > And where is the best point to transfer this information from the > bytecode CFG to the machinecode CFG? The SelectionDAGBuild phase is the only place where the precise relationship between the BasicBlock CFG and the MachineBasicBlock CFG is known. It would also be possible to do the transfer in a later phase, though that would require a fair amount of guesswork to determine how the two CF...

...lated mypass.cpp file; task 3(instantiation of the pass class) should be done in LinkAllPasses.h; task 4(registration of the pass into the PassRegistry) should be done by INITIALIZE_PASS class LiveVariables : public MachineFunctionPass is a case of point. For a built-into codegen/MachineCode pass, task 1 should be done in Passes.h; task 2 should be done in the related mypass.cpp file; task 3 should be done in LLVMTargetMachine.cpp task 4 should be done by INITIALIZE_PASS class IntervalAnalylsis: public MachineFunctionPass is a case in point. I hav...

Hi, Thanks again. >>> during step 2, we read *.bc code and find dummy BB and put some >>> meaningless machinecode, here, we cannot put some illegal machince >>> code, otherwise, step 3 goes to fail. >> >> Yes, you are correct -- if you want to create illegal code you need to >> not use system as. What you need is the ability for llc to create >> object files with native code...

...al ones ? TIA, Dominique Torette. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Dominique Torette via llvm-dev Sent: jeudi 29 mars 2018 15:48 To: llvm-dev at lists.llvm.org Subject: [llvm-dev] Mapping virtual registers to physical registers Hi, In the context of MachineCode custom inserter, I'm trying to enforce the mapping of virtual register to a physical one. According to the documentation https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers<https://clicktime.symantec.com/a/1/VD92eMlNQNYWvTHMFGJ6d9CoI8TWzptcPQ9N_WgcsEc=?...

...> LLVMGetFirstTarget/LLVMGetNextTarget and whatever can be extracted > from them > > * --calc > Test Core.h irbuilding and possibly executionengine. Create a module > with a function evaluating the specified aritmetic expression. > Possibly generating machinecode and executing. > > anders > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...al Message ----- From: Qiuyu Zhang To: llvmdev at cs.uiuc.edu Sent: Wednesday, May 11, 2005 7:32 PM Subject: RE:RE: Question about inserting instructions Hi, Thanks again. >>> during step 2, we read *.bc code and find dummy BB and put some >>> meaningless machinecode, here, we cannot put some illegal machince >>> code, otherwise, step 3 goes to fail. >> >> Yes, you are correct -- if you want to create illegal code you need to >> not use system as. What you need is the ability for llc to create >> object files with na...

PHI nodes within machine code were originally used by the Sparc back-end but they turned out not to be necessary. Instead, LLVM phis are lowered to copy instructions in the machine code (I believe this happens just after instruction selection). As far as I know, the machine PHI nodes are not used by the x86 back-end and you shouldn't need them if you insert the right copies. --Vikram

...ce registers appropriately, if possible. The SparcV9 backend does not implement the 'select' instruction directly, it is lowered by the LowerSelect pass before V9 instruction selector. Furthermore, V9 has a conditional move instruction which some other architectures lack, so they need the MachineCode PHI nodes to work with the target-independent register allocator. > As far as I know, the machine PHI nodes are not used by the x86 > back-end and you shouldn't need them if you insert the right copies. The x86 currently uses PHI nodes because it uses the target-independent register al...

Hi Travis, ... > LLVM is still very relevant to Python because of projects like Numba --- but you > should know that PyPy is no longer using LLVM and Unladen Swallow has not been > worked on for several years. The future of LLVM and Python I think is very > bright --- especially for the scientific and data-analysis user-base. thanks for your interesting email. Do you understand

I like the idea, but I find the name confusing; I think it should have `llvm-c` or `c-api` somewhere in the name. This could also serve as a simple example of using the API. -- Sean Silva On Mon, Sep 23, 2013 at 4:00 PM, Anders Waldenborg <anders at 0x63.nu> wrote: > Moving this to llvmdev. > > On Fri, Sep 20, 2013 at 08:26:41AM +0200, Anders Waldenborg wrote: > > >

...an existing operand is not a good practice. If you want to make significant changes to an instruction, it's usually better to build a new one and remove the old one. Hope this helps, -Krzysztof On 3/29/2018 8:47 AM, Dominique Torette via llvm-dev wrote: > Hi, > > In the context of MachineCode custom inserter, I’m trying to enforce the > mapping of virtual register to a physical one. > > According to the documentation > https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers > > There are two ways: the direct one and the indirect on...