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...wanted to import an untemplated version of the RegionInfo > pass first, as it was easier to review. > > @ether. Do you think you could port your templated version of the > RegionInfo pass to trunk? RegionInfo need PostDominatorTree and DominanceFrontier, do us have DominanceFrontier for MachineBB? > > Tobi > -- best regards ether

On 2007-03-18, at 03:22, Lang Hames wrote: > Is there a recommended way to find the final block (the one with > successors={}) in a machine function? This isn't a property of the CFG in the general case. However, the UnifyFunctionExitNodes transformation/analysis provides it. From getAnalysis<UnifyFunctionExitNodes>().getReturnBlock(), you can visit the basic block

Hi, I need to do an inverse-depth-first iteration over the basic blocks in a machine function (i.e. starting from the last block and following predecessor edges) for a liveness analysis I'm writing. idf_iterator seems like it's almost the class I need, but it starts at the first block in the function at present, rather than the last one (because of the specialisiation of GraphTraits for

...gt; > > ------------------------------------------------------------------------------------------------------- > I'll be honest and say I don't really know how to add the operands > properly to BuildMI. I figured out the following so far > MachineInstrBuilder thing = BuildMI(MachineBB, Position in MBB , > DebugLoc(not sure what this accomplishes), TII->get( X86 instruction I > want), where instruction result goes) > > this has .add(MachineOperand) > .addReg(X86::a reg macro) > .addIMM(a constant like 0x8) > and a few mo...

The size suffix thing is a weird quirk in our assembler I should look into fixing. Instructions in at&t syntax usually have a size suffix that is often optional For example: add %ax, %bx and addw %ax, %bx Are equivalent because the register name indicates the size. but for an instruction like this addw $1, (%ax) There is nothing to infer the size from so an explicit suffix is

the proposed architecture (chris) doesn't seem to attack the phase ordering problem. through having independent instruction selection, instruction scheduling, and register allocation phases faciliate a modular design, but i believe the phase-coupled code generator generator high quality code on many architectures. espeically in the embedded system like a media/dsp processors with very limited