Displaying 2 results from an estimated 2 matches for "lwp_cfg".
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2012 Mar 23
7
LWP Interrupt Handler
I am adding interrupt support for LWP, whose spec is available at
http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can
specify an interrupt vector in LWP_CFG MSR; the interrupt will be
triggered when event buffer overflows. For HVM guests, I want to
re-inject this interrupt back into the guest VM. Here is one idea
similar to virtualized PMU: It first registers a special interrupt
handler (say on vector 0xf6) using set_intr_gate(). When triggered, th...
2013 Sep 23
11
[PATCH v4 0/4] x86/HVM: miscellaneous improvements
The first and third patches are cleaned up versions of an earlier v3
submission by Yang.
1: Nested VMX: check VMX capability before read VMX related MSRs
2: VMX: clean up capability checks
3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation
4: x86: make hvm_cpuid() tolerate NULL pointers
Signed-off-by: Jan Beulich <jbeulich@suse.com>