search for: lwarx

Hi, I want to take an intrinsic function, and get the PowerPC back end to emit: loop: lwarx ... add ... stwcx. ... bne- loop I can successfully emit: lwarx ... add ... stwcx. ... How do I emit a label and a branch instruction? Thanks, Brent

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:",...

...n { > + let Uses = [CR0] in { > + let Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > + .addReg(ptrA).addReg(ptrB); > + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > + .addReg(incr).addReg(dest); > + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); > &g...

...CR0] in { >> + let Uses = [R0] in >> + def ATOMIC_LOAD_ADD_I32 : Pseudo< >> >> The "let Uses = [R0]" is not needed. The pseudo instruction will be >> expanded like this later: >> >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) >> + .addReg(ptrA).addReg(ptrB); >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) >> + .addReg(incr).addReg(dest); >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) >> + .addReg(PPC::R0).addReg(ptrA).ad...

...the lowering if possible; the pseudo instructions are only used in three places, so it shouldn't be a huge change. I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP however: how do I do that? FWIW the code it needs to emit is: ; inputs: ptr, oldval, newval loop: lwarx $tmp, 0, $ptr cmpw $oldval, $tmp bne- exit stwcx. $newval, 0, $ptr bne- loop exit: ... Cheers, Gary -- http://gbenson.net/

...NPHasChain]>; // Instructions to support dynamic alloca. def SDTDynOp : SDTypeProfile<1, 2, []>; @@ -530,23 +546,35 @@ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; -// Atomic operations. -def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX, - [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + l...

...pseudo instructions > are only used in three places, so it shouldn't be a huge change. > I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP > however: how do I do that? FWIW the code it needs to emit is: > > ; inputs: ptr, oldval, newval > loop: > lwarx $tmp, 0, $ptr > cmpw $oldval, $tmp > bne- exit > stwcx. $newval, 0, $ptr > bne- loop > exit: > ... > > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________________________ > LLVM Developers...

...NPHasChain]>; // Instructions to support dynamic alloca. def SDTDynOp : SDTypeProfile<1, 2, []>; @@ -530,23 +546,34 @@ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; -// Atomic operations. -def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX, - [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + l...

...es = [R0] in > >> + def ATOMIC_LOAD_ADD_I32 : Pseudo< > >> > >> The "let Uses = [R0]" is not needed. The pseudo instruction will be > >> expanded like this later: > >> > >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > >> + .addReg(ptrA).addReg(ptrB); > >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > >> + .addReg(incr).addReg(dest); > >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > >> + .addReg...

...: +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_LOAD_ADD_I32 : Pseudo< The "let Uses = [R0]" is not needed. The pseudo instruction will be expanded like this later: + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + .addReg(ptrA).addReg(ptrB); + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) + .addReg(incr).addReg(dest); + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); The second instruction defines R...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...NPHasChain]>; // Instructions to support dynamic alloca. def SDTDynOp : SDTypeProfile<1, 2, []>; @@ -530,23 +546,34 @@ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; -// Atomic operations. -def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX, - [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + l...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

...NPHasChain]>; // Instructions to support dynamic alloca. def SDTDynOp : SDTypeProfile<1, 2, []>; @@ -530,23 +546,34 @@ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; -// Atomic operations. -def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX, - [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + l...

...t; +def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline >>>>>> +def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline >>>>>> +def FWB : FuncUnit; // Write-back unit for the F pipeline >>>>>> + >>>>>> +def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used >>>>>> + // to make sure that no lwarx/stwcx. >>>>>> + // instructions are issued while another >>>>>> + // lwa...

Hello, Gary > I'm trying to figure out how to add the instructions required for > llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch > attached) Applied, thanks! > but the other two (CMP_UNRESw and STWCX) require multiple > instructions: > > let Defs = [CR0] in { > def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), > "stwcx. $rS, $dst\n\tbne- La${...

On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > $label), > "cmpw $rA, $rB\n\tbne- La${label}_exit", > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > $label)]>; > } > > ...and I can't figure out the syntax for that. Any suggestions? Hi

...k); +} + +/* + * This returns the old value in the lock, so we succeeded + * in getting the lock if the return value is 0. + */ +static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock) +{ + unsigned long tmp, token; + + token = LOCK_TOKEN; + __asm__ __volatile__( +"1: " PPC_LWARX(%0,0,%2,1) "\n\ + cmpwi 0,%0,0\n\ + bne- 2f\n\ + stwcx. %1,0,%2\n\ + bne- 1b\n" + PPC_ACQUIRE_BARRIER +"2:" + : "=&r" (tmp) + : "r" (token), "r" (&lock->slock) + : "cr0", "memory"); + + return tmp; +} + +static inl...