search for: lwait_for_data

...example from here: > > > > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html > > > > Which is correct? > > FWIW, I agree with John here. The example I'd give for the unexpected > behaviour allowed in the spec is: > > .Lwait_for_data: > ldr x0, [x3] > cbz x0, .Lwait_for_data > ldnp x2, x1, [x0] > > where another thread first writes to a buffer then tells us where that > buffer is. For a normal ldp, the address dependency rule means we > don't need a barrier or acquiring load to ensure we see...

...center.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html >>> > >>> > Which is correct? >>> >>> FWIW, I agree with John here. The example I'd give for the unexpected >>> behaviour allowed in the spec is: >>> >>> .Lwait_for_data: >>> ldr x0, [x3] >>> cbz x0, .Lwait_for_data >>> ldnp x2, x1, [x0] >>> >>> where another thread first writes to a buffer then tells us where that >>> buffer is. For a normal ldp, the address dependency rule means we >>> don...

On Wed, Jan 13, 2016 at 10:32 AM, John Brawn <John.Brawn at arm.com> wrote: > *What about non-x86 architectures?* > > > > Architectures such as ARMv8 support non-temporal instructions and require > barriers such as DMB nshld to order loads and DMB nshst to order stores. > > > > Even ARM's address-dependency rule (a.k.a. the ill-fated >

...a/CJACGJJF.html >>>>> > >>>>> > Which is correct? >>>>> >>>>> FWIW, I agree with John here. The example I'd give for the unexpected >>>>> behaviour allowed in the spec is: >>>>> >>>>> .Lwait_for_data: >>>>> ldr x0, [x3] >>>>> cbz x0, .Lwait_for_data >>>>> ldnp x2, x1, [x0] >>>>> >>>>> where another thread first writes to a buffer then tells us where that >>>>> buffer is. For a normal ldp, the a...