Displaying 6 results from an estimated 6 matches for "lstartup_write_cr4".
2020 Aug 24
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...s(+)
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 08412f308de3..4622940134a5 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
orl $X86_CR4_LA57, %ecx
1:
#endif
+
+ ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
+
+ /* Early exception handling uses FSGSBASE on APs */
+ orl $X86_CR4_FSGSBASE, %ecx
+
+.Lstartup_write_cr4:
movq %rcx, %cr4
/* Setup early boot stage 4-/5-level pagetables. */
--
2.28.0
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...b/arch/x86/kernel/head_64.S
> index 08412f308de3..4622940134a5 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
> orl $X86_CR4_LA57, %ecx
> 1:
> #endif
> +
> + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> +
> + /* Early exception handling uses FSGSBASE on APs */
> + orl $X86_CR4_FSGSBASE, %ecx
How is this supposed to work?
Alternatives haven't run that early yet and that piece of code looks
like this:
ffffffff81000067: eb 06...
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...b/arch/x86/kernel/head_64.S
> index 08412f308de3..4622940134a5 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
> orl $X86_CR4_LA57, %ecx
> 1:
> #endif
> +
> + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> +
> + /* Early exception handling uses FSGSBASE on APs */
> + orl $X86_CR4_FSGSBASE, %ecx
How is this supposed to work?
Alternatives haven't run that early yet and that piece of code looks
like this:
ffffffff81000067: eb 06...
2020 Aug 31
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...8412f308de3..4622940134a5 100644
> > --- a/arch/x86/kernel/head_64.S
> > +++ b/arch/x86/kernel/head_64.S
> > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
> > orl $X86_CR4_LA57, %ecx
> > 1:
> > #endif
> > +
> > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> > +
> > + /* Early exception handling uses FSGSBASE on APs */
> > + orl $X86_CR4_FSGSBASE, %ecx
>
> How is this supposed to work?
>
> Alternatives haven't run that early yet and that piece of code looks
> like this:...
2020 Aug 24
96
[PATCH v6 00/76] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is the new version of the SEV-ES client enabling patch-set. It is
based on the latest tip/master branch and contains the necessary
changes. In particular those ar:
- Enabling CR4.FSGSBASE early on supported processors so that
early #VC exceptions on APs can be handled.
- Add another patch (patch 1) to fix a KVM frame-size build
2020 Jul 24
86
[PATCH v5 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is a rebased version of the latest SEV-ES patches. They are now
based on latest tip/master instead of upstream Linux and include the
necessary changes.
Changes to v4 are in particular:
- Moved early IDT setup code to idt.c, because the idt_descr
and the idt_table are now static
- This required to make stack protector work early (or