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lshr
2007 Mar 22
1
[LLVMdev] Backend: 2 address + 17bit immediate
...l form.
Clearly I also need a way to load a 32 bit constant value into a register
in order to be able to address more than 64K of memory. I know the PPC
does something similar ...
So for example for SABRE this instruction output would perform the
necessary ...
MOVri %a, HI16(32 bit constant)
LSHri %a,16
ORri %a, LO16(same 32 bit constant)
LD %d, %a // ie load the contents of the memory at the address stored in %a
into register %d
where the HI/LO16 are performed at code generation by LLVM. I'm a little
confused as to how to specify this as a pattern in tablegen syntax, even
with the P...