search for: ls_ucode_img_desc

Displaying 11 results from an estimated 11 matches for "ls_ucode_img_desc".

2016 Nov 02
0
[PATCH v3 06/15] secboot: add low-secure firmware hooks
...define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -}; - - -/** - * struct ls_ucode_img_desc - descriptor of firmware image - * @descriptor_size: size of this descriptor - * @image_size: size of the whole image - * @bootloader_start_offset: start offset of the bootloader in ucode image - * @bootloader_size: size of the bootloader - * @bootloader_imem_offset: start off set of the bootlo...
2016 Nov 02
0
[PATCH v3 14/15] secboot: abstract LS firmware loading functions
...n_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, + const struct ls_ucode_img *_img, u64 wpr_addr, void *_desc) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); struct acr_r352_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + const struct ls_ucode_img_desc *pdesc = &_img->ucode_desc; u64 base, addr_code, addr_data; base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; @@ -162,29 +162,46 @@ struct hsflcn_acr_desc { * Low-secure blob creation */...
2016 Nov 02
0
[PATCH v3 12/15] secboot: remove unneeded ls_ucode_img member
...ob, img->lsb_header.ucode_off, diff --git a/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h b/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h index 0518371a287c..3d8c42e11847 100644 --- a/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h +++ b/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h @@ -173,7 +173,6 @@ struct ls_ucode_img_desc { * @node: to link within lsf_ucode_mgr * @falcon_id: ID of the falcon this LS firmware is for * @ucode_desc: loaded or generated map of ucode_data - * @ucode_header: header of the firmware * @ucode_data: firmware payload (code and data) * @ucode_size: size in bytes of data in ucode_...
2016 Oct 27
15
[PATCH v2 00/14] Secure Boot refactoring
This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the
2016 Nov 02
15
[PATCH v3 00/15] Secure Boot refactoring
This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the
2016 Dec 14
18
[PATCH v5 0/18] Secure Boot refactoring
Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA
2016 Oct 11
10
[PATCH 0/8] Secure Boot refactoring
Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send
2016 Nov 21
33
[PATCH v4 0/33] Secure Boot refactoring / signed PMU firmware support for GM20B
This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,
2016 Feb 24
0
[PATCH v3 10/11] secboot/gm200: add secure-boot support
...define LSF_IMAGE_STATUS_COPY 1 +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 +#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 +}; + + +/** + * struct ls_ucode_img_desc - descriptor of firmware image + * @descriptor_size: size of this descriptor + * @image_size: size of the whole image + * @bootloader_start_offset: start offset of the bootloader in ucode image + * @bootloader_size: size of the bootloader + * @bootloader_imem_offset: start off set of the bootlo...
2016 Feb 24
11
[PATCH v3 00/11] nouveau: add secure boot support for dGPU and Tegra
New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a
2016 Dec 06
9
[PATCH 0/8] Falcon library
This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon