search for: ls_ucode_img_build

The last goto looks spurious because it releases less resources than the previous one. Also free 'img->sig' if 'ls_ucode_img_build()' fails. Fixes: 9d896f3e41a6 ("drm/nouveau/secboot: abstract LS firmware loading functions") Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr> --- v2: update topic only free 'img->sig' if 'ls_ucode_img_build()' fails --- drivers/gpu/...

...ilding the image and descriptor on-the-fly, as you can see from gm200/gr: gm200/gr/fecs_bl.bin gm200/gr/fecs_data.bin gm200/gr/fecs_inst.bin gm200/gr/fecs_sig.bin The bl, data, and inst files are loaded and combined into an image while the corresponding descriptor is built. This is done in the ls_ucode_img_build() function. The main reason for doing this is there is that for a given GPU generation, the _bl and _inst files are very likely going to be exactly the same, with only the data and signature varying. Splitting the sections allow us to symlink identical files. For instance, gr/gm200 weights 61K...

...00/gr: >> >> gm200/gr/fecs_bl.bin >> gm200/gr/fecs_data.bin >> gm200/gr/fecs_inst.bin >> gm200/gr/fecs_sig.bin >> >> The bl, data, and inst files are loaded and combined into an image while the >> corresponding descriptor is built. This is done in the ls_ucode_img_build() >> function. >> >> The main reason for doing this is there is that for a given GPU generation, >> the _bl and _inst files are very likely going to be exactly the same, with >> only the data and signature varying. Splitting the sections allow us to >> symlink id...

...bin >>>> gm200/gr/fecs_inst.bin >>>> gm200/gr/fecs_sig.bin >>>> >>>> The bl, data, and inst files are loaded and combined into an image while >>>> the >>>> corresponding descriptor is built. This is done in the >>>> ls_ucode_img_build() >>>> function. >>>> >>>> The main reason for doing this is there is that for a given GPU >>>> generation, >>>> the _bl and _inst files are very likely going to be exactly the same, >>>> with >>>> only the data and...

...0/gr/fecs_sig.bin >>>>>> >>>>>> The bl, data, and inst files are loaded and combined into an image >>>>>> while >>>>>> the >>>>>> corresponding descriptor is built. This is done in the >>>>>> ls_ucode_img_build() >>>>>> function. >>>>>> >>>>>> The main reason for doing this is there is that for a given GPU >>>>>> generation, >>>>>> the _bl and _inst files are very likely going to be exactly the same, >>>>...

...the-fly, as you can see from gm200/gr: > > gm200/gr/fecs_bl.bin > gm200/gr/fecs_data.bin > gm200/gr/fecs_inst.bin > gm200/gr/fecs_sig.bin > > The bl, data, and inst files are loaded and combined into an image while the > corresponding descriptor is built. This is done in the ls_ucode_img_build() > function. > > The main reason for doing this is there is that for a given GPU generation, > the _bl and _inst files are very likely going to be exactly the same, with > only the data and signature varying. Splitting the sections allow us to > symlink identical files. For insta...

...>> gm200/gr/fecs_data.bin >>> gm200/gr/fecs_inst.bin >>> gm200/gr/fecs_sig.bin >>> >>> The bl, data, and inst files are loaded and combined into an image while >>> the >>> corresponding descriptor is built. This is done in the >>> ls_ucode_img_build() >>> function. >>> >>> The main reason for doing this is there is that for a given GPU >>> generation, >>> the _bl and _inst files are very likely going to be exactly the same, >>> with >>> only the data and signature varying. Splittin...

...gt;>>>> gm200/gr/fecs_sig.bin >>>>> >>>>> The bl, data, and inst files are loaded and combined into an image >>>>> while >>>>> the >>>>> corresponding descriptor is built. This is done in the >>>>> ls_ucode_img_build() >>>>> function. >>>>> >>>>> The main reason for doing this is there is that for a given GPU >>>>> generation, >>>>> the _bl and _inst files are very likely going to be exactly the same, >>>>> with >>&g...

...g; + u32 sig_size; }; /** diff --git a/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c index 1c32cb0f16f9..40a6df77bb8a 100644 --- a/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c +++ b/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c @@ -91,10 +91,9 @@ ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, */ static int ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, - const char *falcon_name, const u32 falcon_id) + const char *falcon_name) { - const struct firmware *bl, *code, *data; - struct ls...

..._header { * it has the required minimum size. */ static void * -gm200_secboot_load_firmware(struct nvkm_subdev *subdev, const char *name, +gm200_secboot_load_firmware(const struct nvkm_subdev *subdev, const char *name, size_t min_size) { const struct firmware *fw; @@ -456,7 +287,7 @@ ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, * blob. Also generate the corresponding ucode descriptor. */ static int -ls_ucode_img_load_generic(struct nvkm_subdev *subdev, +ls_ucode_img_load_generic(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, const char *falcon...

...* @code: LS firmware code segment + * @data: LS firmware data segment + * @desc: ucode descriptor to be written + * + * Return: allocated ucode image with corresponding descriptor information. desc + * is also updated to contain the right offsets within returned image. + */ +static void * +ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, + const struct firmware *data, struct ls_ucode_img_desc *desc) +{ + struct fw_bin_header *bin_hdr = (void *)bl->data; + struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset; + void *bl_data = (void *)bl->data...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a