Displaying 3 results from an estimated 3 matches for "lr_pending".
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fr_pending
2012 Feb 15
7
[PATCH v3] arm: support fewer LR registers than virtual irqs
...include <xen/errno.h>
#include <xen/softirq.h>
+#include <xen/list.h>
#include <asm/p2m.h>
#include <asm/domain.h>
@@ -45,6 +46,8 @@ static struct {
unsigned int lines;
unsigned int cpus;
spinlock_t lock;
+ uint64_t lr_mask;
+ struct list_head lr_pending;
} gic;
irq_desc_t irq_desc[NR_IRQS];
@@ -247,6 +250,8 @@ static void __cpuinit gic_hyp_init(void)
GICH[GICH_HCR] = GICH_HCR_EN;
GICH[GICH_MISR] = GICH_MISR_EOI;
+ gic.lr_mask = 0ULL;
+ INIT_LIST_HEAD(&gic.lr_pending);
}
/* Set up the GIC */
@@ -345,16 +350,51 @@ int _...
2013 Feb 18
2
[PATCH v2 2/4] xen/arm: do not use is_running to decide whether we can write directly to the LR registers
...p;gic.lock);
/* Disable until next VCPU scheduled */
GICH[GICH_HCR] = 0;
isb();
@@ -480,7 +478,7 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq,
spin_lock_irqsave(&gic.lock, flags);
- if ( v->is_running && list_empty(&v->arch.vgic.lr_pending) )
+ if ( v == current && list_empty(&v->arch.vgic.lr_pending) )
{
i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs);
if (i < nr_lrs) {
--
1.7.2.5
2013 Feb 15
1
[PATCH 3/4] xen/arm: dump gic debug info from arch_dump_domain_info
...rs; i++ )
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ }
+
+ list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight )
+ {
+ printk("Inflight irq=%d\n", p->irq);
+ }
+
+ list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue )
+ {
+ printk("Pending irq=%d\n", p->irq);
+ }
+
+}
+
void __cpuinit init_maintenance_interrupt(void)
{
request_irq(25, maintenance_interrupt, 0, "irq-maintenance", NULL);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index...