Displaying 5 results from an estimated 5 matches for "lr_mask".
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2013 Feb 18
2
[PATCH v2 2/4] xen/arm: do not use is_running to decide whether we can write directly to the LR registers
...h/arm/gic.c
index ac1f939..2d0b052 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -65,11 +65,9 @@ void gic_save_state(struct vcpu *v)
{
int i;
- spin_lock_irq(&gic.lock);
for ( i=0; i<nr_lrs; i++)
v->arch.gic_lr[i] = GICH[GICH_LR + i];
v->arch.lr_mask = this_cpu(lr_mask);
- spin_unlock_irq(&gic.lock);
/* Disable until next VCPU scheduled */
GICH[GICH_HCR] = 0;
isb();
@@ -480,7 +478,7 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq,
spin_lock_irqsave(&gic.lock, flags);
- if ( v->is_runni...
2012 Feb 15
7
[PATCH v3] arm: support fewer LR registers than virtual irqs
...#include <xen/sched.h>
#include <xen/errno.h>
#include <xen/softirq.h>
+#include <xen/list.h>
#include <asm/p2m.h>
#include <asm/domain.h>
@@ -45,6 +46,8 @@ static struct {
unsigned int lines;
unsigned int cpus;
spinlock_t lock;
+ uint64_t lr_mask;
+ struct list_head lr_pending;
} gic;
irq_desc_t irq_desc[NR_IRQS];
@@ -247,6 +250,8 @@ static void __cpuinit gic_hyp_init(void)
GICH[GICH_HCR] = GICH_HCR_EN;
GICH[GICH_MISR] = GICH_MISR_EOI;
+ gic.lr_mask = 0ULL;
+ INIT_LIST_HEAD(&gic.lr_pending);
}
/* Set up the...
2013 Oct 08
3
Re: [PATCH v4 1/9] xen/arm: Implement hvm save and restore
...d masks */
>> + /* (it is not necessary to save/restore them, but LR state can have
>> + * influence on downtime after Live Migration (to be tested)
>> + */
>> + memcpy(ctxt.gic_lr, v->arch.gic_lr, sizeof(ctxt.gic_lr));
>> + ctxt.lr_mask = v->arch.lr_mask;
>> + ctxt.event_mask = v->arch.event_mask;
>> +
>> + /* Save PPI states (per-CPU) */
>> + /* It is necessary if SMP enabled */
>> + vgic_irq_rank_save(&ctxt.ppi_state, &v->arch.vgic.private_irqs);
>>...
2013 Feb 15
1
[PATCH 3/4] xen/arm: dump gic debug info from arch_dump_domain_info
...+ b/xen/arch/arm/gic.c
@@ -677,6 +677,33 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r
}
}
+void gic_dump_info(struct vcpu *v)
+{
+ int i;
+ struct pending_irq *p;
+
+ printk("GICH_LRs (vcpu %d) mask=%llx\n", v->vcpu_id, v->arch.lr_mask);
+ if ( v == gic_running )
+ {
+ for ( i = 0; i < nr_lrs; i++ )
+ printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
+ } else {
+ for ( i = 0; i < nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ }
+...
2013 Sep 26
8
[PATCH v5 0/7] Dissociate logical and gic/hardware CPU ID
Hi,
This is the fifth version of this patch series.
With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If
the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen
relies on it to set the logical ID and the GIC, it won''t be possible to use
Xen with this use case.
This patch series is divided in 3 parts:
- Patch 1: prepare Xen