search for: lowspillslot

I just updated from upstream llvm as of about last Thursday and I'm getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps. It seems that the particular instruction being removed happens to reference an object at stack slot 4. The first spilled register is assigned stack slot 6 so LowSpillSlot == 6. Then, when we try to erase from SpillSlotToUsesMap, we index with a negative number. The instruction being removed is generated by instruction selection, so it is part of the original program: %reg1309<def> = FsMOVLPDrm <fi#4>, 1, %reg0, 0, Mem:LD(8,8) [ZETA + 0] Since we'...

...d from upstream llvm as of about last Thursday and I'm > getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps. > It seems that the particular instruction being removed happens > to reference an object at stack slot 4. The first spilled register is > assigned stack slot 6 so LowSpillSlot == 6. Then, when we try to > erase from SpillSlotToUsesMap, we index with a negative number. > > The instruction being removed is generated by instruction selection, > so it is part of the original program: > > %reg1309<def> = FsMOVLPDrm <fi#4>, 1, %reg0, 0, Mem:LD(8,...

...#39;m > > Codegen can definitely create stack slots during isel lowering. I > don't think you can assume all non-fixed slots are created during > register allocation. Ok, so isn't there a bug in VirtRegMap::RemoveMachineInstrFromMaps since it assumes every stack index is >= LowSpillSlot, which doesn't get set until regalloc spill time? -Dave

...efinitely create stack slots during isel lowering. I >> don't think you can assume all non-fixed slots are created during >> register allocation. > > Ok, so isn't there a bug in VirtRegMap::RemoveMachineInstrFromMaps > since > it assumes every stack index is >= LowSpillSlot, which doesn't get > set until > regalloc spill time? > > -Dave > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiu...