search for: lowrisc

...to funding from a third party, I've recently been able to return to this effort as my main focus. Now feels like a good time to give an update on where the RISCV backend is at, and how you can help. ## Current status * A full, regularly rebased patchset can be found here <https://github.com/lowRISC/riscv-llvm>. * 16 of these patches have been put up for review so far. 7 have been committed, and 8 are awaiting review. * The vast majority of the GCC torture suite compiles and runs at O0, targeting RV32I. 1315 out of 1352 compile and run (32 compile-time failures, 5 run-time failures). * I in...

...here the address of global variables of global scope reside. This model assumes that the distance between the GP and the global data area, GOT and local scope variables is defined at link time. __ Evandro Menezes ◊ SiFive ◊ Austin, TX > On Mar 23, 2020, at 6:20, Sam Elliott <selliott at lowrisc.org> wrote: > > Eli, > > Yep, we’re looking at a ROPI/RWPI model for RISC-V and it is shaking out to be fairly similar to this model (though we’ve only been looking at it for 32-bit RISC-V). > > I suppose how I’m thinking about the difference between a ROPI/RWPI model and th...

On 14 November 2017 at 16:03, Alex Bradbury <asb at lowrisc.org> wrote: > Dear list, > > At the RISC-V BoF at the LLVM Dev Meeting and the longer working > session the day after, those of us working on RISC-V with LLVM decided > it would be worthwhile to schedule regular sync-up calls in order to > better co-ordinate ongoing work betwee...

...e-zcog-spp>. We have created a shared calendar which may help in keeping track, which is accessible at: * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ> * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics> Issues to discuss today include the following: * RISC-V Vector extension code generation: any follow-ups? * Some MC-layer patches are landing * LLDB * LLVM 11 Backports: * PseudoBranch Patch https://reviews.llvm.o...

Hey llvm-dev, What's the best method to test performance of Clang generated executables? Are the nightly tests in test-suite sufficient? I'm looking for publicly available tests/suites with a good breadth of coverage... Thanks, Cam -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 23 November 2017 at 09:38, Alex Bradbury <asb at lowrisc.org> wrote: > On 14 November 2017 at 16:03, Alex Bradbury <asb at lowrisc.org> wrote: >> Dear list, >> >> At the RISC-V BoF at the LLVM Dev Meeting and the longer working >> session the day after, those of us working on RISC-V with LLVM decided >> it would...

...erring to data indirectly through a pointer, but it also changes the ABI to keep the pointer in a reserved register. -Eli From: Evandro Menezes <evandro.menezes at sifive.com> Sent: Friday, March 20, 2020 12:28 PM To: Eli Friedman <efriedma at quicinc.com> Cc: Alex Bradbury <asb at lowrisc.org>; llvm-dev <llvm-dev at lists.llvm.org> Subject: [EXT] Re: [llvm-dev] RISC-V LLVM sync-up call 19 Mar 2020 Hi, Eli. If I’m following correctly, there are two size-limited areas. One area, limited to 2GB, is the “text” area. This contains all the code. Then there’s a “global” area,...

...ber 17th), I'm organising a longer working session. This will be held at a Qualcomm location in San Jose, between approximately 10am-4pm. Anyone interested in contributing to RISC-V support in LLVM projects is incredibly welcome. Food and refreshments will be provided. Please email me at asb at lowrisc.org to confirm attendance. I appreciate that the scheduling may not work for those travelling to the Bay Area just for the Dev Meeting. I've assumed that Tue 17th is likely to be no more likely to be unworkable than the Fri the 20th, but do let me know if you think I'm wrong about that. Thi...

Dear list, At the RISC-V BoF at the LLVM Dev Meeting and the longer working session the day after, those of us working on RISC-V with LLVM decided it would be worthwhile to schedule regular sync-up calls in order to better co-ordinate ongoing work between different developers. This is primarily to sync-up, share blocking issues and so on. I understand something similar was done during the

...in one instruction for the first 500 (?) entries in the GOT. Not sure what would end up with smaller codesize in practice. -Eli From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Evandro Menezes via llvm-dev Sent: Thursday, March 19, 2020 9:19 AM To: Alex Bradbury <asb at lowrisc.org> Cc: llvm-dev <llvm-dev at lists.llvm.org> Subject: [EXT] Re: [llvm-dev] RISC-V LLVM sync-up call 19 Mar 2020 Here's the draft proposal for the compact code model on RV. I'd appreciate your feedback before I propose it to the foundation and go about updating the psABI. Thank...

On Wed, 22 Jan 2020 at 19:55, Chris Lattner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Jan 21, 2020, at 5:00 AM, Alex Bradbury <asb at lowrisc.org> wrote: > >> This all makes sense to me. > > > > That's correct, thanks for the feedback. > > > > I do like the idea from James of having the compiler always spit out a > > note when enabling the experimental extension, warning of its > > expe...

...ing to review the patch, it is here: https://reviews.llvm.org/D66887 Background: While working on the RISC-V backend, we have found it useful to use additional test suites beyond the in-tree Clang and LLVM tests and the LLVM nightly tests, in order to ensure the compiler is correct. Internally at lowRISC, we have been running the GCC C Torture suite [1] using custom scripts in order to ensure the backend can handle these tests as well. The main advantage is that the torture suite provide a corpus of simple executable tests that can relatively easily be minimised to identify the sources of bugs or...

...cog-spp>. I've created a shared calendar which may help in keeping track, which is accessible at: * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ> * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics> Issues to discuss today include the following: * Improving rust code size by not forcing frame pointers <https://github.com/rust-lang/rust/pull/69890> * Compact code model (Evandro) * Update on embedded PIC discu...

Hi all, I am trying to implement statepoints for the AArch64 target and I’m running into the issue where the following bitcode: define i32 addrspace(1)* @test(i32 addrspace(1)* %ptr) gc "statepoint-example" { entry: call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @foo, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %ptr) ret

...on Twitter. I've been at FOSDEM this weekend in Brussels (which is why this week's issue is perhaps a little shorter than usual!). Most talks were recorded and I'll be linking to the videos from the LLVM devroom once they're up. For those interested, you can [see the slides from my lowRISC talk here](https://speakerdeck.com/asb/lowrisc-the-path-to-an-open-source-soc). If you want to chat about the project, you may want to join #lowRISC on irc.oftc.net. ## News and articles from around the web Eli Bendersky has written a useful [introduction to using the llvmlite Python to LLVM bin...

...>>>> >>>> Background: >>>> >>>> While working on the RISC-V backend, we have found it useful to use additional test suites beyond the in-tree Clang and LLVM tests and the LLVM nightly tests, in order to ensure the compiler is correct. Internally at lowRISC, we have been running the GCC C Torture suite [1] using custom scripts in order to ensure the backend can handle these tests as well. >>>> >>>> The main advantage is that the torture suite provide a corpus of simple executable tests that can relatively easily be minimised t...

....com/ske-zcog-spp>. We have a shared calendar which may help in keeping track, which is accessible at: * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ> * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics> Issues to discuss today include the following: * Non-scalable RVV support (Fraser) * Patches we might want to discuss: * Zfh (D90738) * Setrounding/flt_rounds lowering * PrologEpilogInserter floating emergency sp...

On 21 March 2018 at 20:07, Alex Bradbury <asb at lowrisc.org> wrote: > On 23 November 2017 at 09:38, Alex Bradbury <asb at lowrisc.org> wrote: >> On 14 November 2017 at 16:03, Alex Bradbury <asb at lowrisc.org> wrote: >>> Dear list, >>> >>> At the RISC-V BoF at the LLVM Dev Meeting and the longer working...

Hi Devs, since risc-v has a register $tp which is thread pointer. is it possible to have __builtin_thread_pointer for RISC-V? I am not sure what could be corresponding instructions? ./kamlesh

...or implementers or researchers to add their own instructions. In line with the proposed policy for adding a new target (https://reviews.llvm.org/D23162), RISC-V has a clear specification, multiple software models, and multiple FPGA implementations as well as prototype ASICs from various groups. At lowRISC (http://www.lowrisc.org/), inspired by our previous experience with the Raspberry Pi project, we are working towards creating a completely open source RISC-V SoC and producing low-cost development boards around it. Feel free to contact me off-list to discuss lowRISC further. LLVM is a key part of o...