Displaying 1 result from an estimated 1 matches for "lowerxmul_lohi".
2017 Sep 27
0
Custom lower multiple return values
...e second one).
The code I based this on is LowerXALUO in AArch64ISelLowering which returns
a MERGE_VALUES without mutating the ResNo. I’m concerned that AArch64 may
be dropping the carry bit based on the semantics observed above, but don’t
know AArch64 well enough to verify.
SDValue MyTarget::LowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned Opc = Op.getOpcode();
unsigned ResNo = Op.getResNo();
assert(Opc == ISD::UMUL_LOHI || Opc == ISD::SMUL_LOHI);
assert(ResNo == 0 || ResNo == 1);
SDValue Op0 = Op.getOperand(0);
SDV...