search for: lowerselect_cc

Can someone explain how the condition code is passed from the MBlazeTargetLowering::LowerSELECT_CC to MBlazeTargetLowering::EmitCustomSelect custom inserter? In LowerSELECT_CC the condition code is never accessed (Op.GetOperand(4)) and I don't see how it ends up getting correctly passed to the MBlazeTargetLowering::EmitCustomSelect. > SDValue MBlazeTargetLowering::LowerSELECT_CC(SDVa...

...nDAG &DAG, const SparcTargetLowering &TLI) { MachineFunction &MF = DAG.getMachineFunction(); *************** *** 3004,3009 **** --- 3023,3030 ---- hasHardQuad); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, hasHardQuad); + case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG, *this); + case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG, *this); case ISD::VASTART: return LowerVASTART(Op...

...tant(0, VT), OVF); > + SDValue Res = DAG.getNode(ISD::SUB, DL, VT, Arg0, Arg1); > + > + return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); > + } > case ISD::FCOS: > case ISD::FSIN: return LowerTrig(Op, DAG); > case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); > diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll > index 8cf43d1..fddb951 100644 > --- a/test/CodeGen/R600/add.ll > +++ b/test/CodeGen/R600/add.ll > @@ -1,12 +1,12 @@ > -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --...

...ering::LowerOperation(SDValue Op, SelectionDAG &DAG) > + const > +{ > + switch (Op.getOpcode()) { > + default: return AMDILTargetLowering::LowerOperation(Op, DAG); > + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); > + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); > + case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); > + } > +} > + > +SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, > + SelectionDAG &DAG) const > +{ > + unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtV...

...// Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3980,59 +3919,203 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); -...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

.../ Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3981,59 +3920,198 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); -...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...// Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3980,59 +3919,205 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); -...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...// Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_SWAP, VTs, Ops, 3); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3980,59 +3919,198 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); -...