Displaying 7 results from an estimated 7 matches for "lowerpacked".
2004 Nov 17
2
[LLVMdev] LowerPacked pass
Hello,
Our software uses 4 x float vectors a lot, and I pass these to LLVM as
packed types - but when I do the JIT compile it seems that the
LowerPacked pass is never run so the code generation fails. I noticed
that most other passes have a header file with a public createXXXPass()
function so they can be added to the PassManager, but LowerPacked
doesn't have this... What should I do?
m.
PS. Chris, thanks for the feedback on the memory cle...
2004 Nov 17
0
[LLVMdev] LowerPacked pass
On Wed, 17 Nov 2004, Morten Ofstad wrote:
> Our software uses 4 x float vectors a lot, and I pass these to LLVM as
> packed types - but when I do the JIT compile it seems that the
> LowerPacked pass is never run so the code generation fails. I noticed
> that most other passes have a header file with a public createXXXPass()
> function so they can be added to the PassManager, but LowerPacked
> doesn't have this... What should I do?
I just added it. There was no reason to not...
2004 Nov 19
1
[LLVMdev] LowerPacked pass
...Lattner wrote:
> Note that packed support in LLVM is not complete yet. In
> particular, here are some of the big missing pieces:
>
> 1. No code generators can generate vector instructions yet (SSE or
> altivec, for example). This should be fairly easy to add though.
> 2. The lowerpacked pass, which currently converts packed ops into their
> scalar counterparts, has a few limitations:
> A. It does not handle packed arguments to functions
> B. It always lowers all of the way to scalar ops, even if the target
> supports SOME packed types. For example...
2005 May 11
2
[LLVMdev] avoid live range overlap of "vector" registers
...is the
> closest match for your model.
This work needs to be done for SSE code generation, which I think would be of interest to several people (including me)
-- Our front-end generates code that uses packed datatypes a lot and I'm not entirely happy with the current situation
using the LowerPacked pass... If SSE code generation was working, we would use LLVM for a lot more, at the moment we
have a small runtime library with SSE optimized functions for things like trilinear interpolation, but the LLVM
optimizer can't do very much with these functions since they are just external calls....
2005 May 11
0
[LLVMdev] avoid live range overlap of "vector" registers
On Wed, 11 May 2005, Tzu-Chien Chiu wrote:
> On Tue May 10 2005, Chris Lattner wrote:
>> On Tue, 10 May 2005, Morten Ofstad wrote:
>>> Actually, I think it would be better to define the registers as a machine
>>> value type for packed float x4, and providing some 'extract' and 'inject'
>>> instructions to access individual components... There
2005 May 11
2
[LLVMdev] avoid live range overlap of "vector" registers
On Tue May 10 2005, Chris Lattner wrote:
>On Tue, 10 May 2005, Morten Ofstad wrote:
>> Actually, I think it would be better to define the registers as a machine
>> value type for packed float x4, and providing some 'extract' and 'inject'
>> instructions to access individual components... There should also be a
>> 'shuffle' instruction
2004 Dec 03
2
[LLVMdev] [Fwd: Updated LLVM Visual Studio project files]
...gt; RelativePath="..\..\lib\Transforms\Scalar\LowerGC.cpp">
> </File>
> <File
> RelativePath="..\..\lib\Transforms\Scalar\LowerInvoke.cpp">
> </File>
> <File
> RelativePath="..\..\lib\Transforms\Scalar\LowerPacked.cpp">
> </File>
> <File
> RelativePath="..\..\lib\Transforms\Scalar\LowerSelect.cpp">
> </File>
> <File
> RelativePath="..\..\lib\Transforms\Scalar\LowerSwitch.cpp">
> </File>
> <F...