Displaying 10 results from an estimated 10 matches for "lowerload".
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
...My target's
allowsUnalignedMemoryOperations() always returns 'false', and the
setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'.
I'm running into a problem where DAGCombiner is being too clever
for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and
LowerSTORE() routines (which emit between 1 and O(10) SDValues,
depending on alignment information), and then runs DAGCombine. To lower
an i16 STORE that is known to be in the high-addressed 2 bytes of a word
on my little-endian target, I emit and LD4 from the word-aligned address
and a...
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
...MemoryOperations() always returns 'false', and the
>> setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'.
>>
>> I'm running into a problem where DAGCombiner is being too clever
>> for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and
>> LowerSTORE() routines (which emit between 1 and O(10) SDValues,
>> depending on alignment information), and then runs DAGCombine. To lower
>> an i16 STORE that is known to be in the high-addressed 2 bytes of a word
>> on my little-endian target, I emit and LD4 from...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...s() always returns 'false', and the
>>> setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'.
>>>
>>> I'm running into a problem where DAGCombiner is being too clever
>>> for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and
>>> LowerSTORE() routines (which emit between 1 and O(10) SDValues,
>>> depending on alignment information), and then runs DAGCombine. To lower
>>> an i16 STORE that is known to be in the high-addressed 2 bytes of a word
>>> on my little-endian target, I e...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...; allowsUnalignedMemoryOperations() always returns 'false', and the
> setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'.
>
> I'm running into a problem where DAGCombiner is being too clever
> for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and
> LowerSTORE() routines (which emit between 1 and O(10) SDValues,
> depending on alignment information), and then runs DAGCombine. To lower
> an i16 STORE that is known to be in the high-addressed 2 bytes of a word
> on my little-endian target, I emit and LD4 from the word-aligne...
2011 Jul 16
2
[LLVMdev] [RFC] LegalizeDAG support for targets without subword load/store instructions
Hi All,
Some targets don't provide subword (e.g., i8 and i16 for a 32-bit
machine) load and store instructions, so currently we have to
custom-lower Load- and StoreSDNodes in our backends. For examples, see
LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I
believe it's possible to support this lowering in a target-agnostic
fashion in LegalizeDAG.cpp, similar to what is done for
non-naturally-aligned loads and stores using the
allowsUnalignedMemoryAccesses() target hook.
I wanted...
2011 Jul 16
0
[LLVMdev] [RFC] LegalizeDAG support for targets without subword load/store instructions
On 16 Jul 2011, at 03:34, Matt Johnson wrote:
> Hi All,
> Some targets don't provide subword (e.g., i8 and i16 for a 32-bit
> machine) load and store instructions, so currently we have to
> custom-lower Load- and StoreSDNodes in our backends. For examples, see
> LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I
> believe it's possible to support this lowering in a target-agnostic
> fashion in LegalizeDAG.cpp, similar to what is done for
> non-naturally-aligned loads and stores using the
> allowsUnalignedMemoryAccesses() target h...
2007 Dec 20
2
[LLVMdev] random warnings
...and LowerBUILD_VECTOR(llvm::SDOperand,
llvm::SelectionDAG&)’:
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
1690: warning: ‘val’ may be used uninitialized in this function
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp: In
function ‘llvm::SDOperand LowerLOAD(llvm::SDOperand,
llvm::SelectionDAG&, const llvm::SPUSubtarget*)’:
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
563: warning: ‘NewOpC’ may be used uninitialized in this function
2007 Dec 22
0
[LLVMdev] random warnings
...R(llvm::SDOperand,
> llvm::SelectionDAG&)’:
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
> 1690: warning: ‘val’ may be used uninitialized in this function
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp: In
> function ‘llvm::SDOperand LowerLOAD(llvm::SDOperand,
> llvm::SelectionDAG&, const llvm::SPUSubtarget*)’:
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
> 563: warning: ‘NewOpC’ may be used uninitialized in this function
> _______________________________________________
> LLVM Developers maili...
2016 Mar 28
0
RFC: atomic operations on SI+
...CmpSwap.getValue(0), Zero);
> +
> + // Merge return value and Chain
> + SDValue Ret = DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(),
> + Old, CmpSwap.getValue(1));
> + return Ret;
> +}
> +
> SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
> SDLoc DL(Op);
> LoadSDNode *Load = cast<LoadSDNode>(Op);
> diff --git a/lib/Target/AMDGPU/SIISelLowering.h b/lib/Target/AMDGPU/SIISelLowering.h
> index 842fbeb..2f87de1 100644
> --- a/lib/Target/AMDGPU/SIISelLowering.h
> +++...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This