search for: lowerglobaladdress

...%rel(answer) load r1, r1, GRP # r1 <- mem[r1+GRP] What I'm getting at the moment is just this part: load r1, r1, GRP So the movimm is missing. That's because I've added the Pseudo instruction RelAddr and GlobalAddress nodes get converted to RelAddr nodes in LowerGlobalAddress.... They used to get converted to the MVINI node type there prior to adding the RelAddr pseudo inst. It feels like more of this needs to be done in the LowerGlobalAddress function, but I have no idea how to do it there - you seem to only be able to get one instruction out of a lowering like that,...

...t;> >> What I'm getting at the moment is just this part: >> >> load r1, r1, GRP >> >> So the movimm is missing. That's because I've added the Pseudo >> instruction RelAddr and GlobalAddress nodes get converted to RelAddr >> nodes in LowerGlobalAddress.... They used to get converted to the MVINI >> node type there prior to adding the RelAddr pseudo inst. >> >> It feels like more of this needs to be done in the LowerGlobalAddress >> function, but I have no idea how to do it there - you seem to only be >> able to get o...

Hi, I got a forced update when pulling today. If I merge master to a local branch, I get a bunch of add/add conflicts. This same commit exists under several hashes: https://github.com/llvm-project/llvm-project-20170507/commit/687841777ef505 https://github.com/llvm-project/llvm-project-20170507/commit/74725885552 Did someone push -f to the monorepo after doing branch surgery? Maybe there was a

In ARM, the conventional way of setting a register to a 32 bit constant is to use a load: --------------------------------- str: .asciz "Hello World" .text main: ... ldr r0, .L3 .... .L3: .word str ----------------------------------- To implement this, LowerGlobalAddress must add an element to the constant pool (.L3 in the example). How can I implement this? Thanks, Rafael

...ases. This happened to me too. I stole a solution from the other targets - create a wrapper node: def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; Then custom lower ISD::GlobalAddress, converting it to a wrapped TargetGlobalAddress: SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { DebugLoc DL = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Op = DAG.getTargetGlobalAddress(GV, MVT::i32); return DAG.getNode(BfinISD::Wrapper, DL, MVT::i32, Op); } Now you can pattern match on the wrapp...

...tion with direct address mode. It accepts two arguments: source register and address (immediate). This instruction is not available in Mips, but it is in Hexagon, so I copied from Hexagon the following, adapting it to my registers: - In ISelLowering.h: CONST32 and CONST32_GP - In ISelLowering.cpp: LowerGlobalAddress - In TargetObjectFile.cpp: isGlobalInSmallSection - In InstrInfo.td: def SDTmyCONST32 : SDTypeProfile<1, 1, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCi...

Hello, I am learning to write a new backend for LLVM and have a few simple questions. 1) What are the differences between 'constant' and 'targetconstant', 'globaladdress' and 'targetglobaladdress'? It is not clear from the document when and which should be used. 2) On the processor I am working on, there is a 'move reg, mem_addr' instruction. When I try

Hi, I've been looking at the new AVR backend lately, and one issue I've found is that all 'load' IR instructions are matched using the 'ld' AVR instruction, including 'load's for lookup tables generated from switches. On the AVR architecture, RAM and the program image are in completely separated namespaces. There's a distinct 'lpm' (Load from Program

I've got this PseudoOp defined: def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Constraints = "$dst = $addr" in { //, Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs GPRC:$dst), (ins i64imm:$spoff,

....word .BB1_2 ------------------------------------- the address ".JTI1_0" must be in a constant pool: --------------------------------- .xyz .word .JTI1_0 .... ldr r1, .xyz add r0, r0, r1 ldr r0, [r0] bx r0 --------------------------------- I intended to do something similar to LowerGlobalAddress. The problem is that a GlobalAddressSDNode has a getGlobal method, but a JumpTableSDNode does not. How can I get a "Constant *" with "JTI1_0"? Thanks, Rafael

...return DAG.getNode(ISD::SUB, dl, MVT::i32, Op0,DAG.getConstant(-val, MVT::i32)); } } return Op; } SDValue MxmTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch(Op.getOpcode()) { case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op,DAG); case ISD::ADD: return LowerADD(Op,DAG); default: llvm_unreachable("illegal custom lowering operation"); } } Unfortunately, this has absolutely no effect. Th...

...e a solution from the other targets - > create a wrapper node: > > def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; > > Then custom lower ISD::GlobalAddress, converting it to a wrapped > TargetGlobalAddress: > > SDValue > BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG > &DAG) > { > DebugLoc DL = Op.getDebugLoc(); > GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); > > Op = DAG.getTargetGlobalAddress(GV, MVT::i32); > return DAG.getNode(BfinISD::Wrapper, DL, MVT::i32, Op); > } > &...

On Mon, 8 May 2017, Krzysztof Parzyszek via llvm-dev wrote: > You can create the differentiation between objects in the data memory and in > the program memory in LowerGlobalAddress (e.g. you can create different ISD > opcodes that generate these addresses) and then use those to select > corresponding instructions. Right, which is how I also understand Zhai Xiang's suggestion with the link to existing AVR target code. This is already done to some extent, since t...

I've been looking at GlobalAddress lowering strategy recently and was wondering if anyone had any ideas, insights, or experience to share. ## Background When lowering global address, which is typically done in FooTargetLowering::LowerGlobalAddress you have the option of folding in the global offset into the global address or else emitting the base globaladdress and a separate ADD node for the offset. Which is best depends on the references to the base GlobalAddress within the function. AArch64 recently gained a DAGCombine for folding offsets...

...FADD); > setTargetDAGCombine(ISD::FSUB); > setTargetDAGCombine(ISD::FMINNUM); > @@ -1168,6 +1174,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { > SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); > return LowerGlobalAddress(MFI, Op, DAG); > } > + case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG); > case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); > case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); > } > @@ -1680,6 +1687,40 @@ SDValue SITar...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This