search for: lowerformalarg

Indeed, if you remove the i16 regs registration by removing the call to addRegisterClass() it works as expected. But that implies some other problems: You cannot pass i16/32/64 arguments to functions or return data using the register pairs (atm i've only implemented LowerReturn and LowerFormalArgs for testing trivial functions). Passing arguments in i8 regs work as expected, BUT, LLVM wont match potential 16bit instruction patterns because data is contained in 8 bit regs making code twice as big. For example, one 16 bit instruction is copying between reg pairs, so as result of this you g...

Thanks for the reply Jakob, good to know that my assumption that LLVM would split regs into smaller subregs is confirmed to be too optimistic. It would be nice if this case could be handled by LLVM, basically trying to split regs and see if patterns match with the splitted regs before giving an error. About the transformation you mentioned in the selection DAG phase, that was my initial question,