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2006 Aug 14
2
[LLVMdev] bug in CSEMap?
I am having some problems with the generated code having wrong constants in the constant pull. Adding a dump of "C" and "E" in SelectionDAG::getConstantPool I get C: ---------------------------------------------------------- %str = internal constant [12 x sbyte] c"Hello World\00" ; <[12 x sbyte]*> [#uses=1]
2006 Aug 14
0
[LLVMdev] Re: bug in CSEMap?
I think that the problem is in SelectionDAG::getConstantPool itself. Only Alignment and Offset are used in the ID. This causes false aliases. X86TargetLowering::LowerFABS should also be affected. All of its calls to getConstantPool have the same alignment and offset. Best Regards, Rafael
2006 Jul 31
1
[LLVMdev] creating a constant with the address of another constant
In ARM, the conventional way of setting a register to a 32 bit constant is to use a load: --------------------------------- str: .asciz "Hello World" .text main: ... ldr r0, .L3 .... .L3: .word str ----------------------------------- To implement this, LowerGlobalAddress must add an element to the constant pool (.L3 in the example). How can I implement this?
2006 Aug 14
1
[LLVMdev] Re: bug in CSEMap?
...el Esp?ndola wrote: > I think that the problem is in SelectionDAG::getConstantPool itself. > Only Alignment and Offset are used in the ID. This causes false > aliases. Doh. Sorry about that, I just checked in a fix. Please verify that this corrects the problem. > X86TargetLowering::LowerFABS should also be affected. All of its calls > to getConstantPool have the same alignment and offset. I think that this should be okay, but I'll let Evan comment on it. -Chris -- http://nondot.org/sabre/ http://llvm.org/
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
..., false); + SDValue FIST = Vals.first, StackSlot = Vals.second; + assert(FIST.getNode() && "Unexpected failure"); + + // Load the result. + return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), + FIST, StackSlot, NULL, 0); +} + SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); MVT VT = Op.getValueType(); @@ -6555,6 +6593,7 @@ case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); case ISD::FP_TO_SINT: return L...