Displaying 6 results from an estimated 6 matches for "lowerextract_vector_elt".
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
...nd know how to insert and extract
>> elements of
>> a vector through sub-register copies? I'm at a loss how to do this...
>
> You probably want to custom lower the insertelement/extractelement
> operations for the cases you support. Take a look at
> X86TargetLowering::LowerEXTRACT_VECTOR_ELT for some examples of how
> to do
> this.
The issue I'm having is that there is no extract/insert instruction
in the ISA, it's simply based on using subregister operands in
subsequent/preliminary instructions. At the pointer of custom
lowering register allocation has not yet b...
2016 Apr 29
3
Assert in TargetLoweringBase.cpp
This post is related to the following post
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html
I'm still trying to compile a library with clang. But now I'm getting as
assert in
lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT
llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT)
const: Assertion `!VT.isVector() && "No default
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
How can one let the back end know how to insert and extract elements
of a vector through sub-register copies? I'm at a loss how to do this...
--
Christopher Lamb
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2007 Apr 23
0
[LLVMdev] Register based vector insert/extract
...> How can one let the back end know how to insert and extract elements of
> a vector through sub-register copies? I'm at a loss how to do this...
You probably want to custom lower the insertelement/extractelement
operations for the cases you support. Take a look at
X86TargetLowering::LowerEXTRACT_VECTOR_ELT for some examples of how to do
this.
-Chris
--
http://nondot.org/sabre/
http://llvm.org/
2007 Apr 23
0
[LLVMdev] Register based vector insert/extract
...;>> elements of
>>> a vector through sub-register copies? I'm at a loss how to do
>>> this...
>>
>> You probably want to custom lower the insertelement/extractelement
>> operations for the cases you support. Take a look at
>> X86TargetLowering::LowerEXTRACT_VECTOR_ELT for some examples of
>> how to do
>> this.
>
> The issue I'm having is that there is no extract/insert instruction
> in the ISA, it's simply based on using subregister operands in
> subsequent/preliminary instructions. At the pointer of custom
> lowering r...
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
...t;>>> a vector through sub-register copies? I'm at a loss how to do
>>>> this...
>>>
>>> You probably want to custom lower the insertelement/extractelement
>>> operations for the cases you support. Take a look at
>>> X86TargetLowering::LowerEXTRACT_VECTOR_ELT for some examples of
>>> how to do
>>> this.
>>
>> The issue I'm having is that there is no extract/insert
>> instruction in the ISA, it's simply based on using subregister
>> operands in subsequent/preliminary instructions. At the pointer of...