Displaying 1 result from an estimated 1 matches for "lowerextload".
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
...load (ldr) and then and the
result with 0xffff to mask out the upper bits.
These are the modifications that I have made to accomplish that:
1. Register the ZEXTLOAD for custom lowering:
setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
2. Implement a custom lowering function:
static SDValue LowerExtLoad(SDValue Op, SelectionDAG &DAG) {
LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode());
ISD::LoadExtType ExtType = LD->getExtensionType();
if (LD->getExtensionType() == ISD::ZEXTLOAD) {
DEBUG(errs() << "ZEXTLOAD\n");
SDValue Chain = LD->getChain();...