search for: lowerdynamic_stackalloc

...umping the RSP); otherwise calling into a function that allocates the memory from the heap [1]. The stack pointer is not modified in the second case. I am trying to implement this by: a. Custom lowering DYNAMIC_ALLOCA in case segmented stacks are enabled. b. Creating a X86ISD::SEG_ALLOCA node in LowerDYNAMIC_STACKALLOC if segmented stacks are enabled. (Right now all LowerDYNAMIC_STACKALLOC on x86 does is check for Windows and lower the call to X86ISD::WIN_ALLOCA). c. Having EmitLoweredSegAlloca do the checks, (calling the external function if needed) and, in both the cases, write the pointer to the allocated mem...

...ng into a function that allocates the memory > from the heap [1]. The stack pointer is not modified in the second case. > > I am trying to implement this by: > > a. Custom lowering DYNAMIC_ALLOCA in case segmented stacks are enabled. > > b. Creating a X86ISD::SEG_ALLOCA node in LowerDYNAMIC_STACKALLOC if > segmented stacks are enabled. (Right now all LowerDYNAMIC_STACKALLOC on > x86 does is check for Windows and lower the call to X86ISD::WIN_ALLOCA). > > c. Having EmitLoweredSegAlloca do the checks, (calling the external > function if needed) and, in both the cases, write the poin...

...That should give you some more test cases. Some "feature" tests can be found inside other directories as well, e.g. msp430 / systemz. Are you planning to add microblaze description to clang? C compiler can speed up testing alot :) More comments: >+SDValue MBlazeTargetLowering:: >+LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { Do you really need this? Expanding dynamic allocas normally ends with stack register adjustment, you don't need anything special here. >+bool MBlazeTargetLowering:: >+SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &amp...

...planning to add microblaze description to clang? C compiler > can speed up testing alot :) I already have a microblaze description in clang but I have not tested it as much so I have not submitted a patch for it yet. > > More comments: >> +SDValue MBlazeTargetLowering:: >> +LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { > Do you really need this? Expanding dynamic allocas normally ends with > stack register adjustment, you don't need anything special here. I was unsure as to whether I needed this or not. I have been taking the approach of removing things conservative...

...esses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions. The issue appears when trying to use the SP in iSelLowering, in particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below: SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); Chain = SP.getValue...

...nstead 2. Moved intrinsics into the MBlaze target directory 3. Used lower case names for registers in the tblgen file 4. Removed tab literals from the generated assembly 5. Added test cases for calling conventions, loops, switches, branches, indirect branches, and indirect function calls 6. Removed LowerDYNAMIC_STACKALLOC 7. Moved address selection into ISelDAGToDAG 8. Updated data layout to only require 4 byte alignment of 64 and 128 bit values. -- Wesley Peck University of Kansas SLDGLaboratory -------------- next part -------------- A non-text attachment was scrubbed... Name: 2010-02-12-mblaze.patch.gz Type: ap...

On Jan 29, 2010, at 9:42 AM, Wesley Peck wrote: > I have been working on a LLVM backend for the MicroBlaze soft-processor: > http://www.xilinx.com/tools/microblaze.htm > http://en.wikipedia.org/wiki/MicroBlaze Very Cool! > Attached is the initial MicroBlaze patch. It does the following: > 1. Adds mblaze as a target in configure and configure.ac > 2. Adds mblaze specific

I have been working on a LLVM backend for the MicroBlaze soft-processor: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze Attached is the initial MicroBlaze patch. It does the following: 1. Adds mblaze as a target in configure and configure.ac 2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and include/llvm/Intrinsics.td 3. Adds mblaze

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following

...return LowerEH_SJLJ_SETJMP(Op, DAG, *this); + case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG, *this); case ISD::VASTART: return LowerVASTART(Op, DAG, *this); case ISD::VAARG: return LowerVAARG(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, *************** *** 3052,3057 **** --- 3073,3085 ---- case SP::SELECT_CC_DFP_FCC: case SP::SELECT_CC_QFP_FCC: return expandSelectCC(MI, BB, SP::FBCOND); + case SP::EH_SJLJ_SETJMP32ri: + case SP::EH_SJLJ_SETJMP32rr: + return emitEHSjLjSetJmp(MI, BB); + case SP::EH_SJ...