search for: lowerbrcond

...ementations for those platforms. The ARM conditions seem to sorta-kinda use predicated instructions (the subject of my next mail). The x86 implementation seems closer to what I want. On closer inspection though, it turns out that the x86 implementation ALWAYS emits a new comparison instruction (in LowerBRCOND and LowerSELECT). baldrick encouraged me to submit bug #3761 (http://llvm.org/bugs/show_bug.cgi?id=3761) as this is suboptimal. My question is how do I achieve my goal? How do I get llvm to recognize the fact that my ALU instructions set the flag register? Thanks for your help, someguy

...ementations for those platforms. The ARM conditions seem to sorta-kinda use predicated instructions (the subject of my next mail). The x86 implementation seems closer to what I want. On closer inspection though, it turns out that the x86 implementation ALWAYS emits a new comparison instruction (in LowerBRCOND and LowerSELECT). baldrick encouraged me to submit bug #3761 (http://llvm.org/bugs/show_bug.cgi?id=3761) as this is suboptimal. My question is how do I achieve my goal? How do I get llvm to recognize the fact that my ALU instructions set the flag register? Thanks for your help, someguy

...; then erase the cmp. See, for example, ARMBaseInstrInfo::optimizeCompareInstr. > > Another, you make a dedicated target-specific ISel node that produces two results: essentially, one is the result of the arithmetic, and the other is the status register. See, for example, X86TargetLowering::LowerBRCOND. > > I don't think you'd want to try to do anything in Select(); I mean, you could try to pattern-match (cmp x, (add x, y)) or whatever, but you'd probably run into trouble if the add has multiple uses. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm....

I attempt to optimize the use of the ‘CMP’ instruction on my architecture by removing the instruction instances where the Status Register already had the correct status flags. The cmp instruction in my architecture is the typical one that compares two registers, or a register with an immediate, and sets the Status Flags accordingly. I implemented my ‘cmp’ instruction in LLVM by custom lowering

...then erase the cmp. See, for example, ARMBaseInstrInfo::optimizeCompareInstr. > > Another, you make a dedicated target-specific ISel node that produces two results: essentially, one is the result of the arithmetic, and the other is the status register. See, for example, X86TargetLowering::LowerBRCOND. > > I don't think you'd want to try to do anything in Select(); I mean, you could try to pattern-match (cmp x, (add x, y)) or whatever, but you'd probably run into trouble if the add has multiple uses. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.ll...

...SDValue DescAddr, SDLoc DL, @@ -2677,7 +2761,8 @@ AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); case ISD::BRCOND: return LowerBRCOND(Op, DAG); case ISD::BR_CC: return LowerBR_CC(Op, DAG); - case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG); + case ISD::GlobalAddress: return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : + LowerGlobalAddressELF(Op, DAG); case...