Displaying 6 results from an estimated 6 matches for "lowerbr_cc".
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
...te loops.
Can you please explain what is happening? It sounds like a bug we should
fix.
>
> What is ideal place where I can convert unordered comparison to un
> comparison + OR + ordered comparison ?
> Can I do it by adding required SDNodes ?
> for example I am trying to do it in LowerBR_CC as shown below:
> getFPCCtoMBCC(CC,TCC);
> TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
> Flag = DAG.getNode(XXXISD::FCMP, dl, MVT::Glue, LHS, RHS,
> TargetCC);
> if (isUnordered) {
> TCC = XXX::COND_UN;
> TargetCC =...
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
..., if any input NaN then return false
> fcmp.ne --> ordered not equal, if any input NaN then return true
> fcmp.ge --> ordered grater equal, if any input NaN then return false
>
> When FPU is not present I need to generate a library call,
>
> so I have added following code in LowerBR_CC function in
> XXXISelLowering.cpp
>
> const XXXSubtarget &STI = static_cast<const XXXSubtarget&>
> (DAG.getSubtarget());
> XXXCC::CondCodes TCC;
> getFPCCtoXXCC(CC,TCC);
> TargetCC = DAG.getConstant(TCC, dl, MVT::i8)...
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
...t --> ordered grater than, if any input NaN then return false
fcmp.ne --> ordered not equal, if any input NaN then return true
fcmp.ge --> ordered grater equal, if any input NaN then return false
When FPU is not present I need to generate a library call,
so I have added following code in LowerBR_CC function in XXXISelLowering.cpp
const XXXSubtarget &STI = static_cast<const XXXSubtarget&>
(DAG.getSubtarget());
XXXCC::CondCodes TCC;
getFPCCtoXXCC(CC,TCC);
TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
if (STI.useHardFloat()) {
/...
2008 Sep 18
4
[LLVMdev] Custom Opcodes versus built-in opcodes
...my backend. These opcodes are then used to
emit a custom set of instructions into the MachineBasicBlock. I've been
able to get one to work correctly, however, I've ran into an issue where
my second one is being confused as a FRAMEADDR opcode instead of my
opcode.
DValue InstTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG& DAG){
MVT VT = Op.getValueType();
SDValue Chain = Op.getOperand(0);
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Jump = Op.getOperand(4);
bool logical_nz = getLogicalNZ(cm...
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
...SDLoc DL,
@@ -2677,7 +2761,8 @@ AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
- case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
+ case ISD::GlobalAddress: return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
+ LowerGlobalAddressELF(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAdd...