Displaying 4 results from an estimated 4 matches for "low_sdvalu".
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low_sdvalue
2013 Nov 09
2
[LLVMdev] [Target] Custom Lowering expansion of 32-bit ISD::SHL, ISD::SHR without barrel shifter
...icular subtarget has 16-bit registers at most, so a
32-bit result is not legal. Normally, if you mark this as "Legal" or
"Expand", then it will expand the node into a more nodes as follows in an
example:
shl i32 %a , 2
=> high_sdvalue = (or (shr %b, 14), (shl %c, 2) )
=> low_sdvalue = (shl %b, 2)
where %b would be the lower 16 bits of %a, and %c is the upper 16 bits of
%a.
Since this target doesn't have a barrel shifter, it would be a huge
performance hit to construct the DAG in this way, due to the large number
of right shifts). Thus, I wish to mark ISD::SHL/SHR as &qu...
2013 Nov 10
0
[LLVMdev] [Target] Custom Lowering expansion of 32-bit ISD::SHL, ISD::SHR without barrel shifter
...it registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example:
>
> shl i32 %a , 2
>
> => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )
> => low_sdvalue = (shl %b, 2)
>
> where %b would be the lower 16 bits of %a, and %c is the upper 16 bits of %a.
>
> Since this target doesn't have a barrel shifter, it would be a huge performance hit to construct the DAG in this way, due to the large number of right shifts). Thus, I wish to mark...
2013 Nov 10
2
[LLVMdev] [Target] Custom Lowering expansion of 32-bit ISD::SHL, ISD::SHR without barrel shifter
..., so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example:
>>
>> shl i32 %a , 2
>>
>> => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )
>> => low_sdvalue = (shl %b, 2)
>>
>> where %b would be the lower 16 bits of %a, and %c is the upper 16 bits of %a.
>>
>> Since this target doesn't have a barrel shifter, it would be a huge performance hit to construct the DAG in this way, due to the large number of right shifts). Thus...
2013 Nov 11
0
[LLVMdev] [Target] Custom Lowering expansion of 32-bit ISD::SHL, ISD::SHR without barrel shifter
.... Normally, if you mark this as "Legal" or
> "Expand", then it will expand the node into a more nodes as follows in an
> example:
> >>
> >> shl i32 %a , 2
> >>
> >> => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )
> >> => low_sdvalue = (shl %b, 2)
> >>
> >> where %b would be the lower 16 bits of %a, and %c is the upper 16 bits
> of %a.
> >>
> >> Since this target doesn't have a barrel shifter, it would be a huge
> performance hit to construct the DAG in this way, due to the large n...