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Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT running on ARM Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-d...

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class project this semester. > I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, a...

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for source files in LLVM? > I am doing a build for ARM on an actual ARM device, and > CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been > like 20 minutes or m...

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? I want to use the LLVM JIT on ARM for a class project this semester. I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there

Hi Does there exist a list of relative compile times for source files in LLVM? I am doing a build for ARM on an actual ARM device, and CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been like 20 minutes or more). I don't even get an error. All the files before it compile pretty quickly but this file in particular just won't finish. The version of gcc I have on

...un, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at wso2.com> wrote: > > Puyan, > There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. > > Rajika > > On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: >> >> Hi >> >> Does there exist a list of relative compile times for source files in LLVM? >> I am doing a build for ARM on an actual ARM device, and CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been like 2...

Hi I am interested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLV...

...%eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. > > It's all a bikeshed, but being more consistent with assembly is probably a win. > > -- Sean Silva > > On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > Hi > > A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are res...

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >&...

...remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at lists.llvm.org> wrote: > Hi > > A few of us have discussed enhancing the MIR vregs to include support for > named-vregs. At the moment named regs are only supported for physical > registers and number regs are reserved for vregs. > > We...

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil

...nd $some_symbol are already familiar from typical assembly > syntax and we probably don't want to break that association. > > It's all a bikeshed, but being more consistent with assembly is probably a > win. > > -- Sean Silva > > On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < > llvm-dev at lists.llvm.org> wrote: > >> Hi >> >> A few of us have discussed enhancing the MIR vregs to include support for >> named-vregs. At the moment named regs are only supported for physical >> registers and number regs are reser...

Hi I am not sure if it is possible to do something similar to what the LLVM pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

...like access to a PTX backend for LLVM. :-)<br /> <br /> On Sat, Mar 27, 2010 at 6:28 PM, Ralf Karrenberg (Chareos@gmx.de) wrote:<br /> > <br /> > Hey,<br /> > <br /> > Chris Lattner schrieb: <br /> > > On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: <br /> > > <br /> > >> Hi <br /> > >> <br /> > >> I am interested to know: are there are any LLVM targets in the works <br /> > >> for Nvidia's PTX ISA? <br /> > >> <br /> > >> Also if...

...iew it, build on it, and improve it. Thanks! Best, Erich Ocean P.s. I too would like access to a PTX backend for LLVM. :-) On Sat, Mar 27, 2010 at 6:28 PM, Ralf Karrenberg (Chareos at gmx.de) wrote: > > Hey, > > Chris Lattner schrieb: > > On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > > > >> Hi > >> > >> I am interested to know: are there are any LLVM targets in the works > >> for Nvidia's PTX ISA? > >> > >> Also if anyone knows about Ocelot (a project done by some students at > >> my schoo...

...timization pass. Said process can be extremely laborious, and this is especially true when comparing shaders or compute modules. Important semantic differences are often difficult to spot because of the irregular naming and ordering of instructions. Looking for a solution we have come across Puyan Lotfi's talk at 2018 EuroLLVM on mir-canon (https://www.youtube.com/watch?v=RHT-bh_xo6U). His project inspired us to invest some time into developing a tool called llvm-canon aiming to achieve a very similar goal - a clean and obvious diff but for LLVM IR dumps. Currently the tool is used internally...

...ot;. ## On the mailing lists * Hans Wennborg [reminds us all](http://lists.llvm.org/pipermail/llvm-dev/2017-December/120016.html) that LLVM 6.0.0 will branch this Wednesday 3rd Jan. The current release schedule will see RC1 on Jan 17th, RC2 on Feb 7th, and the final release on Feb 21st. * Puyan Lotfi has [proposed](http://lists.llvm.org/pipermail/llvm-dev/2017-December/119995.html) changing the use of sigils in Machine IR. The proposal is to use `&` for external symbols, `$` for physical registers and `%` for virtual registers. ## LLVM commits * A whole bunch of code has been cleaned up...

Hi For quiet some time I have noticed a function in my FunctionPasses and CallGraphSCCPasses that calls main(). I think this is probably what does all the program initialization, but I was wondering if there is any documentation on how this all works in the context of LLVM? I ask because I haven't been able to search successfully for much documentation, and I don't see the IR code when I