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2013 Mar 14
1
[PATCH] x86/mce: Use MCG_CAP MSR to find out number of banks on AMD
Currently number of error reporting register banks is hardcoded to
6 on AMD processors. This may break in virtualized scenarios when
a hypervisor prefers to report fewer banks that the physical HW
provides.
Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0]
that''s what we should use.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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2014 Mar 25
5
[LLVMdev] Reducing Generic Address Space Usage
This is a follow-up discussion on
http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20140324/101899.html.
The front-end change was already pushed in r204677, so we want to continue
with the IR optimization.
In general, we want to write an IR pass to convert generic address space
usage to non-generic address space usage, because accessing the generic
address space in CUDA and OpenCL is