search for: loadsdnode

Displaying 20 results from an estimated 54 matches for "loadsdnode".

2015 Feb 13
2
[LLVMdev] DAGCombiner::MergeConsecutiveStores
...ed by a little bit of code in the DAGCombiner where it merges loads in MergeConsecutiveStores. Two 16bit loads have been merged to one 32bit load, and two 16bit stores have been combined to one 32bit store. And then the code goes like this: // Replace one of the loads with the new load. LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), SDValue(NewLoad.getNode(), 1)); // Remove the rest of the load chains. for (unsigned i = 1; i < NumElem ; ++i) { // Replace all chain users of the old...
2017 Oct 23
2
EnableFastISel
...been used is done by testing if TM.Options.EnableFastISel is set. For example in SelectionDAGISel::LowerArguments SDB->setValue(&Arg, Res); if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); } Is it in BUG or am I missin...
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
...I believe a for-loop can make it much more readable. (defining memory space patterns in PTXInstrInfo.td for each memory space) ---------------------------------------- def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{  const Value *Src;  const PointerType *PT;  if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&      (PT = dyn_cast<PointerType>(Src->getType())))    return PT->getAddressSpace() == PTX::GLOBAL;  return false; }]>; def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{  const Value *Src;  const PointerType *PT;  if ((Src = cast...
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
...sk out the upper bits. These are the modifications that I have made to accomplish that: 1. Register the ZEXTLOAD for custom lowering: setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom); 2. Implement a custom lowering function: static SDValue LowerExtLoad(SDValue Op, SelectionDAG &DAG) { LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode()); ISD::LoadExtType ExtType = LD->getExtensionType(); if (LD->getExtensionType() == ISD::ZEXTLOAD) { DEBUG(errs() << "ZEXTLOAD\n"); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); DebugLoc...
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
...9;s *volatile* that let you get a new result, you might want to try change some other parameters and check what it turns out. Regards. 2012/12/2 Joseph Pusdesris <joe at pusdesris.com> > > So I think I have made some progress. > SDValue dupVal = consumer->getOperand(OpNo); > LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode(); > > SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), dupVal.getDebugLoc(), > dupVal.getOperand(0), dupVal.getOperand(1), > dupNode->getPointerInfo(), >...
2013 Feb 19
9
[LLVMdev] [RFC] Add Intel TSX HLE Support
...QUIRE or XRELEASE hints This extra target flag is embedded into the SubclassData fields. The following is rationale how such target flags are embedded into SubclassData in SDNode here is the current SDNode class hierarchy of memory related nodes SDNode -> MemSDNode -> LSBaseNode -> LoadSDNode | + -> StoreSDNode + -> AtomicSDNode + -> MemIntrinsicSDNode here is the current SubclassData definitions: bit 0~1 : extension type used in LoadSDNode bit 0 : truncating store in StoreSDNode bit 2~4 : addre...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...est is for equality or unsigned, and all 1 bits of the const are // in the same partial word, see if we can shorten the load. if (DCI.isBeforeLegalize() && N0.getOpcode() == ISD::AND && C1 == 0 && N0.getNode()->hasOneUse() && isa<LoadSDNode>(N0.getOperand(0)) && N0.getOperand(0).getNode()->hasOneUse() && isa<ConstantSDNode>(N0.getOperand(1))) { LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); APInt bestMask; [...] This shouldn't ever do the wrong thing because of...
2012 Dec 02
0
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
So I think I have made some progress. SDValue dupVal = consumer->getOperand(OpNo); LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode(); SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), dupVal.getDebugLoc(), dupVal.getOperand(0), dupVal.getOperand(1), dupNode->getPointerInfo(), dupNod...
2009 Aug 01
0
[LLVMdev] RFC: SDNode Flags
...t; So what if we replace Volatile/NonTemporal with a single bitvector? > There's not a lot of room in SubclassData (it also holds alignment > information) so maybe this should be another member on MemSDNode. > That will increase the size of MemSDNode, so we need to consider > that. LoadSDNode, which inherits from MemSDNode is the largest SDNode. With the current SDNode allocation strategy, making it bigger will increase the allocation needed for all nodes. > > The constructor could look something like this: > > MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryV...
2012 Dec 01
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
Hi, I am writing an llvm target and I need both loads for isel reasons, but I am struggling to find the right way. I have been trying to use DAG.getLoad() to make a copy, then just change the operand in the consumers, but I cannot seem to get all of the arguments needed for that function in order to make the copy. Any help would be great, thanks! -Joe -------------- next part -------------- An
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something s...
2009 Jul 31
4
[LLVMdev] RFC: SDNode Flags
...ease the size of MemSDNode, so we need to consider that. The constructor could look something like this: MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT, const Value *srcValue, int SVOff, unsigned alignment, unsigned flags); and called like this: new (N) LoadSDNode(..., isVolatile|isNonTemporal); Thoughts? -Dave
2012 Dec 02
0
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
...t, you might > want to try change some other parameters and check what it turns out. > > Regards. > > 2012/12/2 Joseph Pusdesris <joe at pusdesris.com> > > > > So I think I have made some progress. > > SDValue dupVal = consumer->getOperand(OpNo); > > LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode(); > > > > SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), > dupVal.getDebugLoc(), > > dupVal.getOperand(0), > dupVal.getOperand(1), > > dupNode->getPoi...
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
...ange some other parameters and check what it turns out. >> >> Regards. >> >> 2012/12/2 Joseph Pusdesris <joe at pusdesris.com> >> > >> > So I think I have made some progress. >> > SDValue dupVal = consumer->getOperand(OpNo); >> > LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode(); >> > >> > SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), >> > dupVal.getDebugLoc(), >> > dupVal.getOperand(0), >> > dupVal.getOperand(1), >> >...
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
Hi Eli, On 07/27/2011 04:59 PM, Eli Friedman wrote: > On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson > <johnso87 at crhc.illinois.edu> wrote: >> Hi All, >> I'm writing a backend for a target which only supports 4-byte, >> 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and >> STORE nodes in TargetISelLowering.cpp to take advantage of
2007 Jan 06
1
[LLVMdev] Custom load/store code: determining offset or alignment
...ffset and check its alignment as a predicate in the tblgen files? If so, this would likely take care of the normal case if the POD is on the stack and writing patterns is a lot easier than custom selecting or lowering. Q2: Is there any way to determine a POD's offset based on a LoadSDNode and StoreSDNode's data? Currently, LoadSDNode::getBasePtr (and StoreSDNode::getBasePtr) can return something back, but how do I access the operand's offset (and hence, alignment) relative to a base register? Q3: There are three variants of load (and store) for the SPU. Two...
2010 Feb 10
2
[LLVMdev] Metadata
...should we avoid them? > > Is there any reason we would not want to support metadata on SDNodes, > other than the cost of implementing it? We don't necessarily need to do that > now. I'm just asking the question with future possibilities in mind. I think that adding a bit to LoadSDNode and StoreSDNode would make sense. -Chris
2009 Aug 03
2
[LLVMdev] RFC: SDNode Flags
On Saturday 01 August 2009 15:12, Dan Gohman wrote: > LoadSDNode, which inherits from MemSDNode is the largest > SDNode. With the current SDNode allocation strategy, making it > bigger will increase the allocation needed for all nodes. Ok. > > new (N) LoadSDNode(..., isVolatile|isNonTemporal); > > > > Thoughts? > > This sounds r...
2010 Feb 10
3
[LLVMdev] Metadata
On Feb 10, 2010, at 12:42 PM, David Greene wrote: > On Wednesday 10 February 2010 12:58:25 Chris Lattner wrote: > >> I think that adding a bit to LoadSDNode and StoreSDNode would make sense. > > Ok. The consequence is that a number of functions will have to change to > propagate this bit, analogous to what happens with isVolatile. It's > essentially what we do right now here. If everyone's ok with that, I'll go > that r...
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
...; >> >> Regards. >> >> >> >> 2012/12/2 Joseph Pusdesris <joe at pusdesris.com> >> >> > >> >> > So I think I have made some progress. >> >> > SDValue dupVal = consumer->getOperand(OpNo); >> >> > LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode(); >> >> > >> >> > SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), >> >> > dupVal.getDebugLoc(), >> >> > dupVal.getOperand(0), >> >> > dupVal...