search for: loadrs

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

...s */ >+ mov r8=ar.fpsr /* M */ >+ mov r9=ar.csd >+ mov r10=ar.ssd >+ movl r11=FPSR_DEFAULT /* L-unit */ >+ ;; >+ st8 [r16]=r25,16 /* save ar.unat */ >+ st8 [r17]=r26,16 /* save ar.pfs */ >+ shl r18=r18,16 /* compute ar.rsc to be used for >"loadrs" */ >+ ;; >+ st8 [r16]=r27,16 /* save ar.rsc */ >+ adds r17=16,r17 /* skip over ar_rnat field */ >+ ;; >+ st8 [r17]=r31,16 /* save predicates */ >+ adds r16=16,r16 /* skip over ar_bspstore field */ >+ ;; >+ st8 [r16]=r29,16 /* save b0 */ &gt...

...s */ >+ mov r8=ar.fpsr /* M */ >+ mov r9=ar.csd >+ mov r10=ar.ssd >+ movl r11=FPSR_DEFAULT /* L-unit */ >+ ;; >+ st8 [r16]=r25,16 /* save ar.unat */ >+ st8 [r17]=r26,16 /* save ar.pfs */ >+ shl r18=r18,16 /* compute ar.rsc to be used for >"loadrs" */ >+ ;; >+ st8 [r16]=r27,16 /* save ar.rsc */ >+ adds r17=16,r17 /* skip over ar_rnat field */ >+ ;; >+ st8 [r17]=r31,16 /* save predicates */ >+ adds r16=16,r16 /* skip over ar_bspstore field */ >+ ;; >+ st8 [r16]=r29,16 /* save b0 */ &gt...

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

...ar_unat: 0000000000000000 ar_pfs: 8000000000000209 ar_rsc: 0000000000000008 ar_rnat: 0000000000000000 ar_bspstore: a000000100c19030 ar_fpsr: 0009804c8a70433f event_callback_ip: a000000100067a20 pr: 000000000005aa85 loadrs: 0000000000780000 iva: a000000100008000 dcr: 0000000000007e04 r1: a0000001010369a0 r2: 0000000000001000 r3: 8000000000000209 r4: 0000000000000000 r5: 0000000000000000 r6: 0000000000000000 r7: 0000000000000000 r8: a000000100068a70 r9:...

...vti.h : Some macros or routines for VT support on Itanium. > Signed-off-by: Xiantao Zhang <xiantao.zhang at intel.com> > +/* > + * Flushrs instruction stream. > + */ > +#define ia64_flushrs() asm volatile ("flushrs;;":::"memory") > + > +#define ia64_loadrs() asm volatile ("loadrs;;":::"memory") Please put these into include/asm-ia64/gcc_intrin.h > +#define ia64_get_rsc() > \ > +({ > \ > + unsigned long val; > \ > + asm volatile ("mov %0=ar.rsc;;" : "=r"(val) :: "memory"); > \...

...vti.h : Some macros or routines for VT support on Itanium. > Signed-off-by: Xiantao Zhang <xiantao.zhang at intel.com> > +/* > + * Flushrs instruction stream. > + */ > +#define ia64_flushrs() asm volatile ("flushrs;;":::"memory") > + > +#define ia64_loadrs() asm volatile ("loadrs;;":::"memory") Please put these into include/asm-ia64/gcc_intrin.h > +#define ia64_get_rsc() > \ > +({ > \ > + unsigned long val; > \ > + asm volatile ("mov %0=ar.rsc;;" : "=r"(val) :: "memory"); > \...

Hi. This patchset implements xen/ia64 domU support. Qing He and Eddie Dong also has been woring on pv_ops so that I want to discuss before going further and avoid duplicated work. I suppose that Eddie will also post his own patch. So reviewing both patches, we can reach to better pv_ops interface. - I didn't changed the ia64 intrinsic paravirtulization abi from the last post. Presumably it

Hi. This patchset implements xen/ia64 domU support. Qing He and Eddie Dong also has been woring on pv_ops so that I want to discuss before going further and avoid duplicated work. I suppose that Eddie will also post his own patch. So reviewing both patches, we can reach to better pv_ops interface. - I didn't changed the ia64 intrinsic paravirtulization abi from the last post. Presumably it

Hi. This patchset implements ia64/xen domU support based on ia64/pv_ops frame work which was sent as another patchest. Changes from take 5 are rebased to Linux 2.6.26-rc3, bug fix ivt.S paravirtualization and multi entry point support. I believe these patches can be applied to the linux ia64 repository. This patchset does the followings. - Some preparation work. Mainly importing header files to

Hi. This patchset implements ia64/xen domU support based on ia64/pv_ops frame work which was sent as another patchest. Changes from take 5 are rebased to Linux 2.6.26-rc3, bug fix ivt.S paravirtualization and multi entry point support. I believe these patches can be applied to the linux ia64 repository. This patchset does the followings. - Some preparation work. Mainly importing header files to

...the RNAT register since we + // did not flushed the RSE on setjmp. + // + mov r17 = ar.bspstore // get current BSPSTORE + ;; + cmp.ltu p6,p7 = r17, r16 // is it less than BSP of +(p6) br.spnt.few .flush_rse + mov r19 = ar.rnat // get current RNAT + ;; + loadrs // invalidate dirty regs + br.sptk.many .restore_rnat // restore RNAT + +.flush_rse: + flushrs + ;; + mov r19 = ar.rnat // get current RNAT + mov r17 = r16 // current BSPSTORE + ;; +.restore_rnat: + // + // check if RNAT...

This patchset is for more paravirtualization on ia64/pv_ops. - paravirtualize fsys call (fsys.S) by multi compile - paravirtualize gate page (gate.S) by multi compile - support save/restore For this purpose, the followings needs to be paravirtualized - ar.itc instruction - sched_clock() This is because timer may changed before/after saving/restoring. For convenience the working full

This patchset is for more paravirtualization on ia64/pv_ops. - paravirtualize fsys call (fsys.S) by multi compile - paravirtualize gate page (gate.S) by multi compile - support save/restore For this purpose, the followings needs to be paravirtualized - ar.itc instruction - sched_clock() This is because timer may changed before/after saving/restoring. For convenience the working full

This patchset is for more paravirtualization on ia64/xen domU. - paravirtualize fsys call (fsys.S) by multi compile - paravirtualize gate page (gate.S) by multi compile - support save/restore For this purpose, the followings needs to be paravirtualized - ar.itc instruction - sched_clock() This is because timer may changed before/after saving/restoring. For convenience the working full

This patchset is for more paravirtualization on ia64/xen domU. - paravirtualize fsys call (fsys.S) by multi compile - paravirtualize gate page (gate.S) by multi compile - support save/restore For this purpose, the followings needs to be paravirtualized - ar.itc instruction - sched_clock() This is because timer may changed before/after saving/restoring. For convenience the working full

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.