Displaying 3 results from an estimated 3 matches for "loadnop".
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loadno3
2007 Jan 10
0
[LLVMdev] Pattern matching questions
...6InstrSSE.td as an example.
>
>
> Another good example is the PPC backend, which has the exact same issue
> for integer constants.
Actually, for SPU, not quite the same:
def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val),
"ilhu $rT, $val", LoadNOP,
[(set GPRC:$rT, immZExt16:$val)]>;
def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val),
"iohl $rT, $val", LoadNOP,
[(set GPRC:$rT, immZExt16:$val)]>;
Thus, you can't really do as the PPC does, viz:
(...
2007 Jan 09
2
[LLVMdev] Pattern matching questions
On Tue, 9 Jan 2007, Evan Cheng wrote:
>> - How does one deal with multiple instruction sequences in a pattern?
>> To load a constant is a two instruction sequence, but both
>> instructions only take two operands (assume that r3 is a 32-bit
>> register):
>>
>> ilhu $3, 45 # r3 = (45 << 16)
>> iohl $3, 5 # r3 |= 5
2007 Jan 11
1
[LLVMdev] Pattern matching questions
...gt;> Another good example is the PPC backend, which has the exact same
>> issue
>> for integer constants.
>
> Actually, for SPU, not quite the same:
>
> def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val),
> "ilhu $rT, $val", LoadNOP,
> [(set GPRC:$rT, immZExt16:$val)]>;
>
> def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val),
> "iohl $rT, $val", LoadNOP,
> [(set GPRC:$rT, immZExt16:$val)]>;
>
> Thus, you can't reall...