search for: loadlatency

> In particular, the LoadLatency is used in defaultDefLatency: > > /// Return the default expected latency for a def based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return...

...ass describes load instructions InstrItinData<BR, [InstrStage<1, [Slot0]>]> .............................. ]>; def MyTargetModel : SchedMachineModel { // Max issue per cycle == bundle width. let IssueWidth = 2; let Itineraries = MyTargetItineraries; let LoadLatency = 2; } Nowhere in my itinerary description it says that load instruction takes 2 cycles. In the code I couldn't find a path (but I could have missed) how a value from LoadLatency propagates to a load instruction? So how does the packetzer and the scheduler know that a load instruction latency...

...output. >> >> Do you know what could be the problem? Am I missing something? To give >> you a full disclosure, I'm using LLVM 3.5 and at the moment I can't >> switch to the latest version. >> >> Any help is appreciated. >> > > I think that the LoadLatency is used as a last resort when there is no > itinerary available for a given instruction. In your case, there is one > and so the LoadLatency is ignored, and instead the latency from the > itinerary is used. > > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a...

...use it is designed to directly query the fields in the SchedMachineModel tablegen class using another hook to select high latency ops: virtual bool isHighLatencyDef(int opc) const; Instructions that are not high latency default to one cycle. Example: def GenericModel : SchedMachineModel { let LoadLatency = 4; let HighLatency = 10; } If it really helps, you could redeclare defaultDefLatency as a virtual hook and override it. (2) The "old" style of pipeline itineraries. This is closest to the old behavior. If an itinerary is defined, you get to override two hooks: virtual int TargetIn...

...SchedMachineModel SchedModel = ?; } // Cortex-A9 machine model for scheduling and other instruction cost heuristics. def CortexA9Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. let MicroOpBufferSize = 56; // Based on available renamed registers. let LoadLatency = 2; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. let MispredictPenalty = 8; // Based on estimate of pipeline depth. let Itineraries = CortexA9Itineraries; // FIXME:...

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

...to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16; // This flag is set to allow the scheduler to assign a default model to // unrecognized opcodes. let CompleteModel = 0; } def WriteALU : SchedWrite; def WriteBranch : SchedWrite; let SchedModel = MyTargetModel in { // SLOT0 can handles everything def Slot...