search for: loadi16

...pe of instruction in my InstrInfo.td and the relevant entry for this addressing mode is: def IdxI16 : IdxPB2Inst<opcode, AddrModeIdxI16, (outs), (ins memsrc:$mem), !strconcat (str, "\t[$mem]\t; IdxI16"), [(store (OpNode (loadi8 (loadi16 addrIAny:$mem))), (loadi16 addrIAny:$mem))>; where loadi8 and loadi16 are PatFrags that match an i8 and i16 load respectively and OpNode is, in this case, the "not" PatFrag. Pointers are 16-bit by the way. During instruction selection, this pattern...

...10, "load", OpInfo_I64, II_LOAD1 >; defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >; defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >; defm LOADF32 : LoadOp< 0b1001010, "load", OpInfo_F32, II_LOAD1 >; defm LOADI16 : LoadOp< 0b1001010, "load", OpInfo_I16, II_LOAD1 >; defm LOADI8 : LoadOp< 0b1001010, "load", OpInfo_I8, II_LOAD1 >; I tried replacing 'load' with 'LOADI64' in the patter, like this: def: Pat<(LOADI64 (XSTGADDR_NORMAL tglobaladdr:$addr)),...

Maybe I didn't describe the question very well. I want to match these patterns: (and (mul node:$val0, node:$val1)) (and (add node:$val0, node:$val1)) (and (sub node:$val0, node:$val1)) (and (udiv node:$val0, node:$val1)) into "four" different machines instructions, respectively: MUL_AND ADD_AND SUB_AND UDIV_AND That is, this machine is capable of doing an

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote: > >> I've got this PseudoOp defined: >> >> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>; >> def XSTGRELADDR :