search for: loadexcl

...5928887.html>. In that case, spills will surely clear the reservation. There also seem to be documented and very strict forward progress constraints for ARMv8-M. See https://static.docs.arm.com/ddi0553/ah/DDI0553A_h_armv8m_arm.pdf p207 """ Forward progress can only be made using LoadExcl/StoreExcl loops if, for any LoadExcl/StoreExcl loop within a single thread of execution if both of the following are true: • There are no explicit memory accesses, pre-loads, direct or indirect register writes, cache maintenance instructions, SVC instructions, or exception returns between the Load-...

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary