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2014 May 29
3
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
Hi Philip,
On 29 May 2014 17:03, Philip Reames <listmail at philipreames.com> wrote:
> I have some reservations about this proposal. I don't have anything
> particularly concrete, but the idea of supporting both LL/SC and atomicrwm
> in the IR concerns me from a complexity perspective.
Well, I'll start by saying my particular optimisation use case looks
like it's not