Displaying 3 results from an estimated 3 matches for "load_input".
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ldap_input
2016 Mar 28
0
RFC: atomic operations on SI+
...;1, 2,
> + [SDTCisVT<0, v2i32>, // return value (should be i32)
> + SDTCisVT<1, i64>, // address
> + SDTCisVT<2, v2i32> // src followed by cmp
> + ]>,
> + [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
> +>;
> +
> def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
> SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
> SDTCisVT<3, i32>]>
> diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstruction...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...the GPU
> +// hardware does automatically. This function can be used to check if
> +// an opcode falls into this category.
> +bool AMDGPU::isPlaceHolderOpcode(unsigned opcode)
> +{
> + switch (opcode) {
> + default: return false;
> + case AMDGPU::RETURN:
> + case AMDGPU::LOAD_INPUT:
> + case AMDGPU::LAST:
> + case AMDGPU::MASK_WRITE:
> + case AMDGPU::RESERVE_REG:
> + return true;
> + }
> +}
> +
> +bool AMDGPU::isTransOp(unsigned opcode)
> +{
> + switch(opcode) {
> + default: return false;
> +
> + case AMDGPU::COS_r600:
>...