Displaying 2 results from an estimated 2 matches for "load32p_8z".
2009 Mar 15
5
[LLVMdev] Overlapping register classes
...registers:
def D : RegisterClass<"Bfin", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]>;
def P : RegisterClass<"Bfin", [i32], 32, [P0, P1, P2, P3, P4, P5, SP, FP]>;
For instance, a zero-extending byte load needs the address in a P-reg
and can only load a D-reg:
def LOAD32p_8z: F1<(outs D:$dst), (ins P:$ptr),
"$dst = B[$ptr] (Z);",
[(set D:$dst, (zextloadi8 P:$ptr))]>;
Some instructions work on all registers:
def GR : RegisterClass<"Bfin", [i32], 32,
[R0, R1, R2, R3, R4, R5, R6, R7,
P0, P1, P2,...
2009 Mar 16
0
[LLVMdev] Overlapping register classes
...t;Bfin", [i32], 32, [R0, R1, R2, R3, R4, R5,
> R6, R7]>;
> def P : RegisterClass<"Bfin", [i32], 32, [P0, P1, P2, P3, P4, P5,
> SP, FP]>;
>
> For instance, a zero-extending byte load needs the address in a P-reg
> and can only load a D-reg:
>
> def LOAD32p_8z: F1<(outs D:$dst), (ins P:$ptr),
> "$dst = B[$ptr] (Z);",
> [(set D:$dst, (zextloadi8 P:$ptr))]>;
>
> Some instructions work on all registers:
>
> def GR : RegisterClass<"Bfin", [i32], 32,
> [R0, R1, R2, R3, R4...