search for: load32imm

...i32mem:$a), "move $dst, $a;", [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>; I don't quite understand what the semantics of Pat in general. Could you please explain what def : Pat<(BfinWrapper (i32 tglobaladdr:$addr)), (LOAD32imm tglobaladdr:$addr)>; means? And I totally agree it would be better if someone can explain why the Wrapper is needed here. Regards, P.B. On Sun, Apr 19, 2009 at 11:01 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On 20/04/2009, at 07.35, Peter Bacon wrote: > >...

...sterClass<"Bfin", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, P0, P1, P2, P3, P4, P5, SP, FP, I0, I1, I2, I3, M0, M1, M2, M3, B0, B1, B2, B3, L0, L1, L2, L3]>; For instance, I can load an arbitrary 32-bit constant or globaladdr/externalsym into any register: def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src), "$dst.H = HI($src); $dst.L = LO($src);", [(set GR:$dst, imm:$src)]>; I think I am stretching the code generator beyond its capability by doing this. As far as I can tell, instruction selection is...

...oc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Op = DAG.getTargetGlobalAddress(GV, MVT::i32); return DAG.getNode(BfinISD::Wrapper, DL, MVT::i32, Op); } Now you can pattern match on the wrapper: def : Pat<(BfinWrapper (i32 tglobaladdr:$addr)), (LOAD32imm tglobaladdr:$addr)>; If you think this is overly complicated, I agree. Does anybody know why this is necessary? /jakob

...egisters. I compile this function: define void @i56_ls(i56 %x) nounwind { store i56 %x, i56* @i56_s ret void } And get this initial machine code: Live Ins: %R0 %R1 %reg1025D<def> = MOVE %R1 %reg1024D<def> = MOVE %R0 %reg1026D<def> = MOVE %reg1025D %reg1027P<def> = LOAD32imm <ga:i56_s> %reg1028D<def> = SRLd %reg1025D, 16 %reg1029D16L<def> = EXTRACT_SUBREG %reg1026D, 1 %reg1030P<def> = ADDimm7 %reg1027P, 4 STORE16pi %reg1029D16L, %reg1030P, Mem:ST(2,4) [i56_s + 4] STORE8p_imm16 %reg1028D, %reg1027P, 6, Mem:ST(1,2) [i56_s + 6] STORE32p %reg1...

Hello, I am learning to write a new backend for LLVM and have a few simple questions. 1) What are the differences between 'constant' and 'targetconstant', 'globaladdress' and 'targetglobaladdress'? It is not clear from the document when and which should be used. 2) On the processor I am working on, there is a 'move reg, mem_addr' instruction. When I try

...2, > [R0, R1, R2, R3, R4, R5, R6, R7, > P0, P1, P2, P3, P4, P5, SP, FP, > I0, I1, I2, I3, M0, M1, M2, M3, > B0, B1, B2, B3, L0, L1, L2, L3]>; > > For instance, I can load an arbitrary 32-bit constant or > globaladdr/externalsym into any register: > > def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src), > "$dst.H = HI($src); $dst.L = LO($src);", > [(set GR:$dst, imm:$src)]>; > > I think I am stretching the code generator beyond its capability by > doing this. As far as I can tell, in...

..._ls(i56 %x) nounwind { > store i56 %x, i56* @i56_s > ret void > } > > And get this initial machine code: > > Live Ins: %R0 %R1 > %reg1025D<def> = MOVE %R1 > %reg1024D<def> = MOVE %R0 > %reg1026D<def> = MOVE %reg1025D > %reg1027P<def> = LOAD32imm <ga:i56_s> > %reg1028D<def> = SRLd %reg1025D, 16 > %reg1029D16L<def> = EXTRACT_SUBREG %reg1026D, 1 > %reg1030P<def> = ADDimm7 %reg1027P, 4 > STORE16pi %reg1029D16L, %reg1030P, Mem:ST(2,4) [i56_s + 4] > STORE8p_imm16 %reg1028D, %reg1027P, 6, Mem:ST(1,2) [i...