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load32
2011 Oct 21
0
[LLVMdev] Problems with live intervals and spilling when having sub registers?
...304d:1)[304d,320d:0) 0 at 304d 1 at 288d
Later %vreg6 and %vreg64 are merged. The register allocator spills
%vreg6 (fi#14) and the resulting code is
%r0l<def> = mv_any16 65535
Store32FI %r0<kill>, <fi#14>; mem:ST4[FixedStack14] %r0h<def> = mv_any16
16383 %r1<def> = Load32FI <fi#14>; mem:LD4[FixedStack14]
So the whole %r0 register is spilled to the stack after only one half is
written, and then what is supposed to go into the other half is never
used. Instead the previously written value is reloaded from the stack.
I don't know what the live intervals abo...