Displaying 7 results from an estimated 7 matches for "load26".
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load2
2015 Sep 20
2
simplifycfg not happening?
...; preds = %vector.body10,
%vector.body10.preheader
%index13 = phi i64 [ 0, %vector.body10.preheader ], [ %index.next21.1,
%vector.body10 ], !dbg !25
%17 = getelementptr inbounds double, double* %a, i64 %index13, !dbg !24
%18 = bitcast double* %17 to <2 x double>*, !dbg !26
%wide.load26 = load <2 x double>, <2 x double>* %18, align 8, !dbg !26
%19 = getelementptr double, double* %17, i64 2, !dbg !26
%20 = bitcast double* %19 to <2 x double>*, !dbg !26
%wide.load27 = load <2 x double>, <2 x double>* %20, align 8, !dbg !26
%21 = fmul <2 x dou...
2015 Sep 20
2
simplifycfg not happening?
...0.preheader
>> %index13 = phi i64 [ 0, %vector.body10.preheader ], [ %index.next21.1,
>> %vector.body10 ], !dbg !25
>> %17 = getelementptr inbounds double, double* %a, i64 %index13, !dbg !24
>> %18 = bitcast double* %17 to <2 x double>*, !dbg !26
>> %wide.load26 = load <2 x double>, <2 x double>* %18, align 8, !dbg !26
>> %19 = getelementptr double, double* %17, i64 2, !dbg !26
>> %20 = bitcast double* %19 to <2 x double>*, !dbg !26
>> %wide.load27 = load <2 x double>, <2 x double>* %20, align 8, !dbg !...
2013 Jul 05
0
[LLVMdev] Enabling vectorization with LLVM 3.3 for a DSL emitting LLVM IR
On 07/04/2013 01:39 PM, Stéphane Letz wrote:
> Hi,
>
> Our DSL can generate C or directly generate LLVM IR. With LLVM 3.3, we can vectorize the C produced code using clang with -O3, or clang with -O1 then opt -O3 -vectorize-loops. But the same program generating LLVM IR version cannot be vectorized with opt -O3 -vectorize-loops. So our guess is that our generated LLVM IR lacks some
2013 Jul 04
3
[LLVMdev] Enabling vectorization with LLVM 3.3 for a DSL emitting LLVM IR
Hi,
Our DSL can generate C or directly generate LLVM IR. With LLVM 3.3, we can vectorize the C produced code using clang with -O3, or clang with -O1 then opt -O3 -vectorize-loops. But the same program generating LLVM IR version cannot be vectorized with opt -O3 -vectorize-loops. So our guess is that our generated LLVM IR lacks some informations that are needed by the vectorization passes to
2018 Jan 29
1
Panic: data stack: Out of memory when allocating bytes
...at 0x07816000: load24a ALLOC LOAD
> READONLY CODE HAS_CONTENTS
> ??? 0x7f73f0b17000->0x7f73f0b17000 at 0x07817000: load24b ALLOC
> READONLY CODE
> ??? 0x7f73f0b2a000->0x7f73f0b2a000 at 0x07817000: load25 ALLOC READONLY
> ??? 0x7f73f0d2a000->0x7f73f0d2b000 at 0x07817000: load26 ALLOC LOAD
> HAS_CONTENTS
> ??? 0x7f73f0d2b000->0x7f73f0d2c000 at 0x07818000: load27a ALLOC LOAD
> READONLY CODE HAS_CONTENTS
> ??? 0x7f73f0d2c000->0x7f73f0d2c000 at 0x07819000: load27b ALLOC
> READONLY CODE
> ??? 0x7f73f0d42000->0x7f73f0d42000 at 0x07819000: load28...
2018 Jan 24
2
Panic: data stack: Out of memory when allocating bytes
On Wed, Jan 24, 2018 at 18:55:47 +0100, Thomas Robers wrote:
> Am 23.01.2018 um 20:07 schrieb Josef 'Jeff' Sipek:
> > On Tue, Jan 23, 2018 at 14:03:27 -0500, Josef 'Jeff' Sipek wrote:
> > > On Tue, Jan 23, 2018 at 18:21:38 +0100, Thomas Robers wrote:
...
> > > 1. Do you have any idea what the imap process was doing at the time of the
> > >
2018 Jan 25
0
Panic: data stack: Out of memory when allocating bytes
...16000->0x7f73f0b17000 at 0x07816000: load24a ALLOC LOAD
READONLY CODE HAS_CONTENTS
0x7f73f0b17000->0x7f73f0b17000 at 0x07817000: load24b ALLOC
READONLY CODE
0x7f73f0b2a000->0x7f73f0b2a000 at 0x07817000: load25 ALLOC READONLY
0x7f73f0d2a000->0x7f73f0d2b000 at 0x07817000: load26 ALLOC LOAD
HAS_CONTENTS
0x7f73f0d2b000->0x7f73f0d2c000 at 0x07818000: load27a ALLOC LOAD
READONLY CODE HAS_CONTENTS
0x7f73f0d2c000->0x7f73f0d2c000 at 0x07819000: load27b ALLOC
READONLY CODE
0x7f73f0d42000->0x7f73f0d42000 at 0x07819000: load28 ALLOC READONLY
0x7f73f0f...