Displaying 2 results from an estimated 2 matches for "load2048".
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
...ion in lowering stage? some thing like;
addRegisterClass(MVT::v2048i32, &X86::Reg_B);
setOperationAction(ISD::MNLOAD, MVT::v2048i32,
custom);
then in function LowerOperation(SDValue Op, SelectionDAG &DAG)
i should do,
case ISD::MNLOAD: return LOAD2048(Op, Subtarget, DAG);
then i will implement
static SDValue LOAD2048(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG)
{
//dont know the details of this part
but here i plan to encode 2048 elements again in 32 v64i32 but with
different instruction name...
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
hello,
i have a situation where i have to assign the registers to instructions
based on the loop iterations.
for eg..
the registers are:
R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,
R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,
R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.
These registers defined in object Reg_A
These are total 12 registers. will use them contiguously, here i define it
in above mentioned order i.e