Displaying 3 results from an estimated 3 matches for "load12".
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2014 Nov 11
3
[LLVMdev] supporting SAD in loop vectorizer
...8* %pix2, i64 %index
> 2797 %11 = bitcast i8* %10 to <4 x i8>*
> 2798 %wide.load11 = load <4 x i8>* %11, align 1
> 2799 %.sum20 = or i64 %index, 4
> 2800 %12 = getelementptr i8* %pix2, i64 %.sum20
> 2801 %13 = bitcast i8* %12 to <4 x i8>*
> 2802 %wide.load12 = load <4 x i8>* %13, align 1
> 2803 %14 = zext <4 x i8> %wide.load11 to <4 x i32>
> 2804 %15 = zext <4 x i8> %wide.load12 to <4 x i32>
> 2805 %16 = sub nsw <4 x i32> %8, %14
> 2806 %17 = sub nsw <4 x i32> %9, %15
> 2807 %18 = icmp...
2014 Nov 11
4
[LLVMdev] supporting SAD in loop vectorizer
...ex
> > 2797 %11 = bitcast i8* %10 to <4 x i8>*
> > 2798 %wide.load11 = load <4 x i8>* %11, align 1
> > 2799 %.sum20 = or i64 %index, 4
> > 2800 %12 = getelementptr i8* %pix2, i64 %.sum20
> > 2801 %13 = bitcast i8* %12 to <4 x i8>*
> > 2802 %wide.load12 = load <4 x i8>* %13, align 1
> > 2803 %14 = zext <4 x i8> %wide.load11 to <4 x i32>
> > 2804 %15 = zext <4 x i8> %wide.load12 to <4 x i32>
> > 2805 %16 = sub nsw <4 x i32> %8, %14
> > 2806 %17 = sub nsw <4 x i32> %9, %15
> > 2...
2014 Nov 04
3
[LLVMdev] supporting SAD in loop vectorizer
----- Original Message -----
> From: "Renato Golin" <renato.golin at linaro.org>
> To: "Dibyendu Das" <Dibyendu.Das at amd.com>
> Cc: llvmdev at cs.uiuc.edu
> Sent: Tuesday, November 4, 2014 5:23:30 AM
> Subject: Re: [LLVMdev] supporting SAD in loop vectorizer
>
> On 4 November 2014 11:06, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: